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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Analyze HDL file encrypt_1735

haianhle
New Contributor I
1,270 Views

I encrypted the hdl file with encrypt_1735 (dti_phy_ctl_blk.v -> dti_phy_ctl_blk.vp)

"encrypt_1735 dti_phy_ctl_blk.v --language=verilog --quartus" 

then I took that file to analyze and got an error:

311070129_784438032851354_3022861848376745975_n.jpg

Error: Internal Sub-system: QIS, File: /quartus/synth/qis/qis_rtl_stage_utility.cpp, Line: 705

Error: No modules found when analyzing [PATH]/dti_phy_ctl_blk.vp.

 

How can I synthesize encrypted files?

Thanks and best regards

phuongnn0

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7 Replies
ShengN_Intel
Employee
1,255 Views

Hi,


If you already have the encryption key, do the followings:

  1. Encrypt the design with IEEE 1735. Command line used: encrypt_1735 --quartus --language=verilog counter.v
  2. File counter.vp will be generated in the file folder.
  3. Open a new project, add counter.vp in the project. Set it as top-level entity.
  4. Right click on the counter.vp. Select Properties. Ensure the Type: Verilog HDL File.
  5. Run Analysis & Synthesis.


Thanks,

Best Regards,

Sheng


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


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haianhle
New Contributor I
1,224 Views

I have successfully Run Analysis & Synthesis file dti_phy_ctl_blk.vp

But I want to create components from my design so I use Platform Design 

--------

I use Platform Design to create new components

1. I add  dti_phy_ctl_blk.vp

2. Set type Verilog HDL

3. Set Attributes  is Top-Level file

4. Run Analyze HDL Files

 

Then I got that error

Error: Internal Sub-system: QIS, File: /quartus/synth/qis/qis_rtl_stage_utility.cpp, Line: 705

Error: No modules found when analyzing [PATH]/dti_phy_ctl_blk.vp.

 

How can I finish creating a new component.

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ShengN_Intel
Employee
1,192 Views

Hi,


Let me further confirm with expert and get back to you soon. Please allow some time for it.


Thanks,

Best Regards,

Sheng


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ShengN_Intel
Employee
1,079 Views

Hi @haianhle ,

 

Internal expert feedback:

Qsys invokes quartus_syn for the analysis of the HDL files. I don't think Quartus can decrypt unknown encrypted files, so this is expected behavior that it would fail on analysis of encrypted files

 

Thanks,

Best regards,

Sheng

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haianhle
New Contributor I
1,033 Views

I encrypted the hdl file with encrypt_1735(Quartus encrypt tool). So I think it is not unknown encrypted files

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ShengN_Intel
Employee
993 Views

@haianhle Based on internal feedback, unknown encrypted files also include Quartus encrypt tool (encrypt_1735). Feedback as below:

Is the file encrypted with the altera key?

If it is quartus synthesis can analyze it. Otherwise it can't.

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haianhle
New Contributor I
1,000 Views
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