Another 10482 VHDL error

[Altera_Forum]

Hello folks. I am trying for the first time to ease into the Altera MegaWizard DDR3 controller and have written a small VHDL top-level module containing an instance of the DD3 controller from the MegaWizard. When I try to compile the design, Quartus returns several 10482 errors; for example, "Error (10482): VHDL error at TryOutQuartusTop.vhd(212): object "pll_ref_clk" is used but not declared." Each of the errors refers to a port on the MegaWizard - generated DDR3 controller. I have searched the VHDL forum but have not found the answer. pl_ref_clk appears in the MegaWizard - generated files, so I do not know how to solve this error. I can follow the pll_ref_clk through the hierarchy, and it is connected. Can any one help?

[Altera_Forum]

that error indicates it is expecting a locally signal that hasnt been decalred. 

 Have you mapped something like this?   signal pll_ref_clk : std_logic; -- this is a local wire pll_ref_clk => pll_ref_clk, -- this maps the port of the entity to the local wire   Your error would come around if you didnt declare the signal locally, even if the port name exists on the component.

[Altera_Forum]

--- Quote Start ---  that error indicates it is expecting a locally signal that hasnt been decalred.  Have you mapped something like this?   signal pll_ref_clk : std_logic; -- this is a local wire pll_ref_clk => pll_ref_clk, -- this maps the port of the entity to the local wire   Your error would come around if you didnt declare the signal locally, even if the port name exists on the component.  --- Quote End ---    Okay, thank you for your reply. You prompted me to notice that I made a silly mistake by attempting to map to a port with "<=" rather than "=>." How embarrassing -- over 20 years of VHDL experience but a few recent years of not doing it.  Problem solved. Thanks a bunch.