Any difference between these processes ?

[Altera_Forum]

Is there any deep meaning behind the "standard" process declaration regarding "en" signal ? : 

  process (clk, rst) begin if (rst = '0') then q1 <= '0'; elsif (rising_edge(clk)) then if (en = '1') then q1 <= D; end if; end if; end process;   I tried to do this in the following way:   process (clk, rst) begin if (rst = '0') then q2 <= '0'; elsif ((rising_edge(clk)) and (en = '1')) then q2 <= D; end if; end process;   and don't see any difference at RTL or Technology Map view...

[Altera_Forum]

I don't think they are different but the second one is not recommended template and is not necessary. 

The tool is smart enough not to gate clock with enable but I don't always trust the software team which made the compilers  Moreover you may not put enable on all registers in the process.

[Altera_Forum]

--- Quote Start ---  Moreover you may not put enable on all registers in the process.  --- Quote End ---    Very simple thing, but I didn't think about it, thanks !

[Altera_Forum]

--- Quote Start ---  The tool is smart enough not to gate clock with enable but I don't always trust the software team which made the compilers  --- Quote End ---    Modern version yes, but older versions maybe not.  Interestingly, newer quartus versions are using the sensitivity list to alter circuit generation to match the RTL more closely, so I wouldnt be surprised if it actually did gate the clock if en was put in the sensitivity list.  As Kaz pointed out, the 2nd method is not recommended, and is not in the RTL coding guidelines written by altera, which they will always use as an excuse when something doesnt work...

[Altera_Forum]

--- Quote Start ---   Interestingly, newer quartus versions are using the sensitivity list to alter circuit generation to match the RTL more closely, so I wouldnt be surprised if it actually did gate the clock if en was put in the sensitivity list.  --- Quote End ---    I don't think "en" signal from my second example is in the sensitivity list...

[Altera_Forum]

--- Quote Start ---  I don't think "en" signal from my second example is in the sensitivity list...  --- Quote End ---    It's not, and with good reason. If you added it, it would simulate is if it was a gated clock. Without it in there, it simulates like a register with clock enable.  My point is, with the tool now able to use sensitivity lists to make different logic, it might just chose between the two options above, depending only on the sensitivity list.