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verilog code problem in VGA 1024x768

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module Sungka2(clk,hcount,vcount,hsync,vsync,R,G,B,clk65,clr,lock,lock1,clk32,SW1); input clk,clr; //input clock 50Mhz input SW1; output lock,clk65,lock1,clk32; output reg R; output reg G; output reg B; output hcount; output vcount; output hsync, vsync; reg hsync,vsync,hblank,vblank,blank; reg hcount; // pixel number on current line reg vcount; // line number wire hsyncon,hsyncoff,hreset,hblankon; // next slide for generation wire vsyncon,vsyncoff,vreset,vblankon; // of timing signals wire next_hb = hreset ? 0 : hblankon ? 1 : hblank; // sync & blank wire next_vb = vreset ? 0 : vblankon ? 1 : vblank; //65 Mhz pixel clock // horizontal: 1344 pixels total // display 1024 pixels per line assign hblankon = (hcount == 1023); // turn on blanking assign hsyncon = (hcount == 1047); // turn on sync pulse 1047 assign hsyncoff = (hcount == 1183); // turn off sync pulse 1183 assign hreset = (hcount == 1343); // end of line (reset counter) 1343 // vertical: 806 lines total // display 768 lines assign vblankon = hreset & (vcount == 767); // turn on blanking assign vsyncon = hreset & (vcount == 776); // turn on sync pulse assign vsyncoff = hreset & (vcount == 782); // turn off sync pulse assign vreset = hreset & (vcount == 805); // end of frame mhz65 ( .areset (clr), .inclk0 (clk), .c0 (clk65), .locked (lock)); mhz32 ( .areset (clr), .inclk0 (clk), .c0 (clk32), .locked (lock1)); always @(posedge clk65) begin hcount <= hreset ? 0 : hcount + 1; hblank <= next_hb; hsync <= hsyncon ? 0 : hsyncoff ? 1 : hsync; // active low vcount <= hreset ? (vreset ? 0 : vcount + 1) : vcount; vblank <= next_vb; vsync <= vsyncon ? 0 : vsyncoff ? 1 : vsync; // active low end always @(posedge clk) begin if (vblank | (hblank & ~hreset)) begin R <= 8'b00000000; G <= 8'b11111111; B <= 8'b11111111; end else begin R <= 8'b11111111; G <= 8'b11111111; B <= 8'b00000000; end end endmodule  

 

The problem is it is not displaying a whole cyan or yellow but rather displaying stripes of partially cyan and yellow and green
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