We currently using quartus ii web edition version 13sp1.
We are trying to deploy a solution for our customer using Altera Cyclone 2 FPGA. However, we are running into a problem related to state transition within one of our modules. Questions:
- FYI, we have a long list of states in the state machine and the state is monitored by an external logic analyzer. Occasionally, the state value captured by the analyzer is not a value set anywhere in the Verilog code. What could be causing this to happen?
- Are there any good debugging tools that can help us troubleshoot this issue easily?
If your state machine has inputs, make sure you buffer (synchronise) these inputs with the clock. Otherwise, your logic network that defines transitions from one state to another could be in a transition and not in a stable state when your state variable is updated.