We currently using quartus ii web edition version 13sp1.
We are trying to deploy a solution for our customer using Altera Cyclone 2 FPGA. However, we are running into a problem related to state transition within one of our modules. Questions:
If your state machine has inputs, make sure you buffer (synchronise) these inputs with the clock. Otherwise, your logic network that defines transitions from one state to another could be in a transition and not in a stable state when your state variable is updated.