How to assign a dual-region clock network in assignment editor?

[jrrguzman]

Hi,

I got Cyclone V SoC design with a parallel port split into two different regional clock networks. This port is driven by a PLL clock and I would like to force the PLL to use a regional clock network in dual-regional mode.

I know how to force a regional network with the assignment editor (by forcing a certain CLKCTRL_R buffer, but I haven't been able to drive an additional CLKCTRL_R to obtain the dual-regional mode.

I've tried something similar as what's described in:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd09282011_171.html

(instead of ~clkctrl I have to use ~CLKENA0) but the method they describe for dual-regional doesn't work (~CLKENA0_d). Quartus says it doesn't exist and ignores the assignment.

Any idea on how to do this?

Kind regards

[Kenny_Tan]

Hi,

Is that possible to attached your simplified project to look into it? What is the error message that you are getting?

Thanks,​

[jrrguzman]

Hi,

It's not an error. The fitter does not recognize the assignment and it does not apply it.

Anyway, I've managed to achieve the desired effect by populating the clock buffer myself and use a "~_Duplicate" modified at the sd1 component to force a dual region clock network. Anyway, I would have liked to be able to do this automatically without using a dedicated clock buffer.

Cheers.