Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Annonces
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.

Array Declaration cases

Altera_Forum
Contributeur émérite II
1 593 Visites

Hi All, 

 

Is there a difference in the following declarations: 

 

case1: 

reg [3:0][7:0] abc; 

case2: 

reg [3:0] abc [7:0]; 

case3: 

reg abc [3:0][7:0]; 

 

What's the difference? 

 

Thank you!
0 Compliments
2 Réponses
Altera_Forum
Contributeur émérite II
725 Visites

Putting dimensions before the variable name is a packed array. packed arrays can only be made of bit types. 

Unpacked arrays have the dimensions after the name. They can be any type. 

 

http://www.asic-world.com/systemverilog/data_types10.html
0 Compliments
Altera_Forum
Contributeur émérite II
725 Visites

Thanks Tricky! 

 

I need to declare a multi-dimension array of enumerated elements...  

 

Could you please take a look in this thread: https://alteraforum.com/forum/showthread.php?t=57903  

 

Thank you again!
0 Compliments
Répondre