Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Discussions

Array Declaration cases

Altera_Forum
Honored Contributor II
‎02-19-2018 07:34 PM
1,589 Views

Hi All, 

 

Is there a difference in the following declarations: 

 

case1: 

reg [3:0][7:0] abc; 

case2: 

reg [3:0] abc [7:0]; 

case3: 

reg abc [3:0][7:0]; 

 

What's the difference? 

 

Thank you!
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎02-19-2018 10:42 PM
721 Views

Putting dimensions before the variable name is a packed array. packed arrays can only be made of bit types. 

Unpacked arrays have the dimensions after the name. They can be any type. 

 

http://www.asic-world.com/systemverilog/data_types10.html
0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎02-19-2018 11:09 PM
721 Views

Thanks Tricky! 

 

I need to declare a multi-dimension array of enumerated elements...  

 

Could you please take a look in this thread: https://alteraforum.com/forum/showthread.php?t=57903  

 

Thank you again!
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.