Hi All,Is there a difference in the following declarations: case1: reg [3:0][7:0] abc; case2: reg [3:0] abc [7:0]; case3: reg abc [3:0][7:0]; What's the difference? Thank you!
Putting dimensions before the variable name is a packed array. packed arrays can only be made of bit types.Unpacked arrays have the dimensions after the name. They can be any type. http://www.asic-world.com/systemverilog/data_types10.html