Array en VHDL

[Altera_Forum]

Hi everybody !  

 I want to add(xor) data with CD in shape array and the result would be S   Can you help me correcting this code :   library ieee;use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity cdm is port ( clk : in std_logic ; rst : in std_logic ; data: in std_logic ; odata: out std_logic ; CD : in std_logic_vector(15 downto 0) ; isis :out integer range 0 to 3 ; S :out std_logic_vector(3 downto 0 )); end entity ; architecture beh of cdm is type tab is array(3 downto 0)of std_logic_vector(15 downto 0); signal i :integer range 0 to 3 ; signal idata :std_logic ; signal itab :tab ; begin code :process(clk,rst) begin if(rst='1')then itab(i)<="0000" ; else if(clk'event and clk='1')then itab(i)<= not(CD(15 downto 12)xor (data)); S(i)<=itab(i); i<= i+1 ; itab(i)<=not(CD (11 downto 8) xor(data)); S(i)<=itab(i); i<=i+1 ; itab(i)<=not( CD(7 downto 4) xor (data)); S(i)<=itab(i); i<=i+1; itab(i)<=not( CD(3 downto 0) xor (data)); S(i)<=itab(i); i<=i+1 ; if i=3 then idata<=data ; end if ; end if ; end if ; end process ; isis<=i; odata<=idata ; end architecture ;   Thank you in advance for your answer

[Altera_Forum]

What is the problem?  

I think, your i signal is never assigned a value. You're missing a loop or something like that to assign a value to i to begin with. Also itab is always assigned the last value. I suggest you think about the code a little more.

[Altera_Forum]

I suggest: 

 inside clocked process if reset then  i <= 0; ... i <= i+1; case i is when 0 => s(0) <=not(CD(15 downto 12)xor (data)); when 1 => s(1) <= ...; when 2 => when 3 =>

[Altera_Forum]

corrected S 

 inside clocked process if reset then  i <= 0; ... i <= i+1; case i is when 0 => s <=not(CD(15 downto 12)xor (data&data&data&data)); when 1 => s <= ...; when 2 => when 3 =>

[Altera_Forum]

You want that I make like that : 

 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity cdm is  --generic (  -- width : natural :=4);  port (  clk : in std_logic ;  rst : in std_logic ;  data: in std_logic ;  odata: out std_logic ;  CD : in std_logic_vector(15 downto 0) ;  isis :out integer range 0 to 3 ;  S :out std_logic_vector(3 downto 0 )); end entity ;  architecture beh of cdm is   --type tab is array(3 downto 0)of std_logic_vector(15 downto 0);    signal i :integer range 0 to 3 ;  signal idata :std_logic ;  --signal itab :tab ;  begin   code :process(clk,rst)  begin   if(rst='1')then   i<="0000" ;  else   if(clk'event and clk='1')then     i<=i+1 ;  case i is   when 0 =>s(0)<=not(CD(15 downto 12) xor (data));  when 1 =>s(1)<=not(CD(11 downto 8) xor (data));  when 2 =>s(2)<=not(CD(7 downto 4) xor (data));  when 3 =>s(3)<=not(CD(3 downto 0) xor (data));    if i=3 then   idata<=data ;  end if ;  end case ;  end if ;  end if ;  end process ;  isis<=i;    odata<=idata ;  end architecture ;   ?? ! Thank you in advance

[Altera_Forum]

try this  

  if(rst='1')then i <= 0 ; elsif(clk'event and clk='1')then i <= i + 1 ; case i is when 0 => s <= not(CD(15 downto 12) xor (data&data&data&data)); when 1 => s <= not(CD(11 downto 8) xor (data&data&data&data)); when 2 => s <= not(CD(7 downto 4) xor (data&data&data&data)); when 3 => s <= not(CD(3 downto 0) xor (data&data&data&data)); odata<=data ; end case ; end if ; end process ; end architecture ;

[Altera_Forum]

I thank that it is necessary to leave the 1st program and inside it will be necessary to make out a will "data" (1 or 0) 

 non ?

[Altera_Forum]

--- Quote Start ---  I thank that it is necessary to leave the 1st program and inside it will be necessary to make out a will "data" (1 or 0)  non ?  --- Quote End ---    I don't think even "Tricky" can understand your post. Why don't you just simulate and adjust things. That is how we all work and learn. write compile simulate and repeat cycle

[Altera_Forum]

There are some errors : 

 Error (10381): VHDL Type Mismatch error at cdmoin.vhd(34): indexed name returns a value whose type does not match "std_ulogic", the type of the target expression Error (10327): VHDL error at cdmoin.vhd(34): can't determine definition of operator ""&"" -- found 0 possible definitions  ?!

[Altera_Forum]

--- Quote Start ---  I don't think even "Tricky" can understand your post. Why don't you just simulate and adjust things. That is how we all work and learn. write compile simulate and repeat cycle  --- Quote End ---    I'm sorry but I don't well understood !

[Altera_Forum]

You didnt copy Kaz's code properly. It compiles just fine for me. 

Like Kaz said - why not try and learn the code yourself, rather than have someone do it for you?

[Altera_Forum]

is that error in this file or another? also as a sidenote, putting your code in code tags improves readability.

[Altera_Forum]

hi guys !! 

 i solved my problem but i have another is near of ""Type Re is array ""   can you help me please !!  """"  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity cdma_testbipo is   port (  clk : in std_logic ;  rst : in std_logic ;  data: in std_logic ;  odata: out std_logic ;  type Re is array(0 to 3)of integer range 0 to 15;  signal CD: Re ;  isis :out integer range 0 to 3 ;  S :out integer range -8 to 7 ); end entity ;  architecture beh of cdma_testbipo is     type RAM is array (0 to 3) of integer range -8 to 7;  signal i :integer range 0 to 3 ;  signal code : RAM;  signal idata :std_logic ;    begin     code(0)<=CD(15 downto 12);  code(1)<=CD(11 downto 8) ;  code(2)<=CD(7 downto 4) ;  code(3)<=CD(3 downto 0) ;  bpsk :process(clk,rst)  begin   if(rst='1')then   i<= 0;  else   if(clk'event and clk='1')then     i<=i+1 ;  if(idata='0') then   s<=-code(i);   else   s<=code(i);  end if;    if(i=3) then   idata<=data;  end if;    end if ;  end if ;  end process ;  isis<=i;    odata<=idata ;  end architecture ;   """""  Thank you

[Altera_Forum]

you cannot declare an array type inside a port declaration. It will need to be in a package