Arrow Cyclone V SoCKit Hard DDR3 Memory controller interface

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Arrow Cyclone V SoCKit Hard DDR3 Memory controller interface

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Hello all,

I have a query with respect to the implementation of the Hard Memory controller + UniPHY interface for the Cyclone V SoCKIT development board (https://www.arrow.com/en/products/sockit/arrow-development-tools/#2pne)

One of the same reference designs provided with the board shows you the use of the soft memory controller. Does anyone here have experience with the Hard Memory controller?

If so, except for checking the "Enable Hard Memory Interface" and "Enable AFI half clock" are there other settings that need to be changed from the implementation of the soft memory controller?

I am attempting at implementing the same design using hard memory controller. Also, please post if you have a simple reference design that does the same.

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