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Hi,
I experience a crash during assembler stage for my design. Attached is the report generated by Quartus. As far i can understand there is an issue with some constraints regarding the IOPLL ip that i use. For the same design the assembler had worked fine before i included an IOPLL ip (very simple pll : one refclk one output, all else defaults) in the constraints i just include 'derive_pll_clocks' and 'derive_clock_uncertainty commands. anybody had similar problem before? i saw some issues with Aria 10 in Quartus but i don't think this is my problem as without the IOPLL i could get a sof file...- Tags:
- FPGA Design Tools
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Thats a tool crash - you'll have to raise a mysupport ticket to find out the cause.
Have you tried using Q16 instead of 15?- Mark as New
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--- Quote Start --- Thats a tool crash - you'll have to raise a mysupport ticket to find out the cause. Have you tried using Q16 instead of 15? --- Quote End --- I think i will ask the support , it is just weird because with the similar design and another (more complex) PLL it doesn't crash. I wonder if there is some assembler parameter that has to be set...
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