Assign all zeroes to unsigned

[Altera_Forum]

Hi, I want to assign all zeroes to an unsigned signal. I've been using ( others => '0' ) for STD_LOGIC_VECTOR signals, but when i attempt to do the same for unsigned, i get an error: 

 Error (10500): VHDL syntax error at top.vhd(222) near text "others"; expecting "(", or an identifier ("others" is a reserved keyword), or unary operator  Does this only work at the declaration of the signal? Can I use it within my process on reset for example? if not, is there another easy way to set a signal to all zeroes? ( i am trying to avoid typing it all out since I plan to change the size of these signals between subsequent runs. )

[Altera_Forum]

Unsigned is a base 10 nuber without a sign. So assigning 0 should work. 

unsigned_sig <= 0;

[Altera_Forum]

--- Quote Start ---  Unsigned is a base 10 nuber without a sign. So assigning 0 should work. unsigned_sig <= 0;  --- Quote End ---    You can't do that because 0 is an integer. Also note that unsigned is binary, not base 10. You need to convert to an unsigned from an integer.  Op <= to_unsigned(0, op'length);  This should also work.  Op <= (others => '0'); The ops problem sounds like a syntax error. Why not post the actual code?

[Altera_Forum]

unsigned type accepts (others => '0'); 

it also accepts comparing with integer type but not assigning to integer type

[Altera_Forum]

--- Quote Start ---  You can't do that because 0 is an integer. Also note that unsigned is binary, not base 10. You need to convert to an unsigned from an integer.  Op <= to_unsigned(0, op'length);  This should also work.  Op <= (others => '0'); The ops problem sounds like a syntax error. Why not post the actual code?  --- Quote End ---    Hi, I have no idea what the problem was but i reverted my code to a previous save and made my changes one by one and it worked! i wish i knew what caused the problem in the first place, but i cant even seem to reproduce it now.