I have a project in Quartus ii. The data captured by an ADC is sent into a filter to filter its high frequencies components of received signal. Then the filtered data is transformed by a FFT module. But the data has period T. ADC won't collect data for a short time at the start of period. The point of FFT is 8192.The number of collected data lesses then 8192, so I have to add some zero at the end of the collected data. The FFT IP core works in burst mode, so i need a asynchronous fifo to buffer the data,named LPF_FIFO. But the rdclk and wrclk of LPF_FIFO is the same.
For example, the number of collected by an ADC is 6500. The asynchronous fifo,LPF_FIFO, is followed by a filter, which buffers the filtered data. Firstly, The 6500 filtered data was written into LPF_FIFO, then I read the 6500 data from LPF_FIFO. i may read only 1000 data ,then the next 6500 data of next period has came. I use a counter to count the number of data read from the LPF_FIFO . when the value of the counter is 6500,i stop read.
this method works in modelsim.But when i program the code into a board,i found the code won't work correctly sometimes in signaltap ii.
the control of LPF_FIFO may failed.
someone can help about how control asynchronous fifo in this condition . The fifo is read when it is written.
