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Hi there,
I needed an asynchronous counter to count the frequencies of ring oscillators. So I built a ripple-counter by concatenating T-type (toggle) flip-flops. Everytime the input "clock" of such a flip-flop changes, the flip-flop changes its output value:entity t_ff is
port (
-- Input ports
q_in : in std_logic;
rst : in std_logic;
-- InOut ports
q_out : inout std_logic
);
end entity t_ff;
architecture logic of t_ff is
begin
process(q_in, rst)
begin
if rst = '1' then
q_out <= '0';
elsif falling_edge(q_in) then
q_out <= q_out xnor q_in;
end if;
end process;
end architecture logic;
To build the ripple-counter, I connected the q-out of one T-flip-flop to the q_in of the next flip-flop. It works as expected, but during compilation with Quartus I get several warnings of the form: Warning (332060): Node: ripple_counter:my_counter|t_ff:\create_other_ff:1:create|q_out~reg0 was determined to be a clock but was found without an associated clock assignment. Is there a way of telling Quartus that it should not be concerned about this? Thanks!
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4 Replies
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Afaik, there are very few warnings in quartus you can really suppress. These usually come about because you're doing something that an FPGA isnt really designed for,
Btw, code appraisal: you shouldnt really read inout ports. The "prefered" method is to declare q_out an out and have an internal local signal. Or switch on the VHDL 2008 compile compatability and you can read out ports (like in verilog), to avoid using inout.- Mark as New
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You need to add create_generated_clock for any new clock that comes out of a register.
Though such method of clocking is not recommended but is possible.- Mark as New
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Thanks for your answers!
Regarding "create_generated_clock": Excuse my ignorance, but in which TCL file would I have to add these commands? Furthermore, by what I was able to find online, I understand that create_generated_clock needs a source clock. So is ripple_counter:my_counter|t_ff:\remaining_ff:1: create|q_out~reg0 the source of ripple_counter:my_counter|t_ff:\remaining_ff:2: create|q_out~reg0 and so forth? Could anybody give me a hint about how to write the complete create_generated_clock command? This is the updated code of the ripple-counter and the T-flip-flop (incorporating the advise by Tricky):
entity t_ff is
port (
-- Input ports
q_in : in std_logic;
rst : in std_logic;
-- Output ports
q_out : out std_logic
);
end entity t_ff;
architecture logic of t_ff is
signal internal_q : std_logic := '0';
begin
q_out <= internal_q;
process(q_in, rst, internal_q)
begin
-- Reset=1 sets the flip flop to 0.
if rst = '0' then
if falling_edge(q_in) then
internal_q <= not internal_q;
end if;
-- reset = 1
else
internal_q <= '0';
end if;
end process;
end architecture logic;
entity ripple_counter is
generic (
bit_length : integer := 26
);
port (
-- Input ports
clock : in std_logic;
reset : in std_logic;
run_counter : in std_logic;
-- Output ports
q : out std_logic_vector((bit_length-1) downto 0)
);
end entity ripple_counter;
architecture logic of ripple_counter is
component t_ff
port (
q_in : in std_logic;
rst : in std_logic;
q_out : out std_logic
);
end component;
-- Input bit for first t_ff.
signal q_0 : std_logic := '0';
signal internal_q : std_logic_vector ((bit_length-1) downto 0);
begin
q <= internal_q;
-- Create first T-FlipFlop.
first_ff: t_ff port map (q_0, reset, internal_q(0));
-- Create (bit_length-2) T-FlipFlops.
remaining_ff: for i in 1 to bit_length-1 generate
create: t_ff port map (internal_q(i-1), reset, internal_q(i));
end generate;
process(clock, run_counter)
begin
if run_counter = '1' then
q_0 <= clock;
else
q_0 <= '0';
end if;
end process;
end architecture logic;
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it is all here
Timing_Analysis_of_Internally_Generated_Clocks_in_Timequest_v2.0.pdf![](/skins/images/7FC17B7B85029576C25F1E43CE255B51/responsive_peak/images/icon_anonymous_message.png)
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