Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Attribute in RTL for Timing Constraints

Maio
Beginner
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Hello,

 

For AMD, I used the following methodology to create timing constraints for registers:

 

RTL Code:

(* some_attribute = "true" *) reg [31:0] config_register;

 

Constraints:

[get_cells -hier -filter {some_attribute =~ true}]

 

The above get_cells command would return the cells from the RTL code I added the attribute to, and then I could add any command on those cells from the constraints files in the build.

 

Is there an equivalent to this for Quartus? I have attempted to run a get_cells command that gets cells based on an attribute but I was unable to solve this.

 

Thanks

 

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Nurina
Employee
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Hi,


Thank you for using Intel Communities.


As far as I know there is no command for this. But you can see the targets that the attributes apply to on the RTL Analyzer in the latest Quartus Pro software: https://www.intel.com/content/www/us/en/docs/programmable/683236/23-2/inspecting-sdc-on-rtl-constraints.html


Regards,

Nurina


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Nurina
Employee
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Hello,


We have not received a reply from you. As such, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

 

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Have a great day!

Best regards,

Nurina W.


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