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Auto gated clock convert to clock enable

NuvKFC
New Contributor I
446 Views

I get a ASIC design which want to be verified on FPGA.

I know Quartus support "Auto gated clock convert to clock enable" recently.

 

Web: https://www.intel.com/content/www/us/en/programmable/quartushelp/15.1/index.htm#verify/da/comp_file_...

 

From the above web, I know that case(1) can completely support  gated clock conversion.

How about case(2)? Can latch-based clock gating work for gated clock conversion?

Should I do formal verification when  "Auto gated clock convert to clock enable" is turned on.

 

How about case(3)?

 

Case(1): Note that enable_a is from the clock_a domain.

assign gated_clock_a=clock_a & enable_a;

assign gated_clock_a=clock_a | enable_a;

 

Case(2): Latch-based clock gating

always@(*) begin

    if (~clock_a )

            enable_a <= enable;

end

 

assign gated_clock_a= clock_a & enable_a ;

 

Case(3): Note that enable_a    is from the clock_a domain.

                Note that enable_a2 is from the gated_clock_a domain.

assign gated_clock_a   = clock_a & enable_a;

assign gated_clock_a2 = gated_clock_a | enable_a2;

 

Thank you very much.

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1 Solution
Nurina
Employee
387 Views

Hi,


Sorry for the late response. From what I know, case 2 is allowed.

You can refer to pages 12-10 to 12-12 of this document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii51006.pdf#pag...


Is case 3 a cascaded clock gating? This only works on certain devices, I think it's best you don't use this method since you're doing ASIC prototyping.


Regards,

Nurina


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6 Replies
NuvKFC
New Contributor I
397 Views

Could someone please tell me the answer? Thank you very much.

Nurina
Employee
388 Views

Hi,


Sorry for the late response. From what I know, case 2 is allowed.

You can refer to pages 12-10 to 12-12 of this document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii51006.pdf#pag...


Is case 3 a cascaded clock gating? This only works on certain devices, I think it's best you don't use this method since you're doing ASIC prototyping.


Regards,

Nurina


NuvKFC
New Contributor I
367 Views

Hi NurinaW,

        Thank you, NurinaW, very much. I understand it. About case 3, a cascaded clock gating, ASIC has different application domain so that there needs a  cascaded clock gating to gate the clock for different IP and for different application domain. So, I can't cancel that.

Nurina
Employee
337 Views

Hi,


It depends on your device. It's supported in Arria® series, Cyclone® II, Cyclone III, Cyclone IV, Stratix® II, Stratix II GX, Stratix III, Stratix IV, and Stratix V devices. 


You can refer to section 2.2.3.5 here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-qpp-design-r...


And this help page; https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#logicops/logicops...


Regards,

Nurina


Nurina
Employee
310 Views

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Regards,
Nurina

P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!

NuvKFC
New Contributor I
294 Views

Hi NurinaW

     OK. Thank you, NurinaW, very much.

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