Automated connectivity check in Quartus Prime Pro

[Pack_of_lone_wolves]

In a considerably big project, there could be multiple HDL module hierarchies, where, in each hierarchy, multiple individual modules have been instantiated.

Suppose

Hierarchy A has following modules: B1, B2, B3.

A -> (B1, B2, B3).

Hierarchy C has: D1, D2, D3.

C -> (D1, D2, D3). 

Suppose an output signal (wire/net) Q from B1 goes to D2 via B1 -> A -> B -> D2, then I can check this connectivity in either post-synthesis RTL Viewer or post-fit technology map viewer. 

I want to write a script such that I specify the source output port at B1 and destination input port at D2 and the script should return TRUE if both ports are found connected post synthesis.

How do I do this in Quartus Prime Pro? 

[KennyTan_Altera]

Unfortunately, we intel do not support/help to write custom tcl scripts.

I will provide this scripts base on the best I can. Let me know if it works for you.

[KennyTan_Altera · Accepted solution]

script

[Pack_of_lone_wolves]

Thank you for answering! I should be coming back in 2 working days to accept this as solution.
I understand that custom script support is too much an ask, but what the demo script provides me is the objects that can then be used in my custom script.

[RichardTanSY_Altera]

May I know if you need further help regarding this case?

Regards,

Richard Tan

[Pack_of_lone_wolves]

No, Thank you for asking. 

[KennyTan_Altera]

As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.