Automatic VHDL Code Generation Programmatically

[Altera_Forum]

We are actually working on a Double Precision IIR filter. We are interested in making a very generic filter which could support variety of functionalities. For some reason, VHDL generics are not superior enough to support this task. We are thinking of adopting an approach where we can generate required VHDL code programmatically: 

 Following are few requirements we have for this tool - allows plugging in already present VHDL entities - allow manipulation of existing VHDL - create customized VHDL code inside VHDL template with entity, architectures etc. - Additionally support test bench generation - Provide memory interfacing - Allow easy future upgrades in IP - Focus on DSP circuits - Optionally allow to verify design  Megawizard in Quartus seems to be using some in-built EDA API to generate custom HDL code. Any idea what sort of libraries or framework Altera uses for VHDL code generation in megawizard?  Besides, I have come across two free tools: vMagic and MyHDL. I am still exploring them.   If you know any other superior tool(open-source) for automatic VHDL code generation manipulation, that would be really nice  Thanks Varun

[Altera_Forum]

The problem is, FPGA designs tend to get quite tight with resources. generated code often produces designs that use a lot more resources than would be the case with something that was hand coded. So you can see the friction here. 

 Mathwoks offer HDL coder that generates generic HDL from simulink designs, but its a bit limited in what it can do. But it can all the things you're asking for.

[Altera_Forum]

I think understand what you are trying to say. Actually I am not looking for High Level Synthesis tool or model based synthesis toolflow.  

 I still want to work at RTL level but instead of handcoding VHDL I am interesting in using some library (Java,Python etc.) in which I could programmatic-ally generate HDL.

[Altera_Forum]

I have seen VHDL generated from Python before, but have not done it myself. At the time, the python just connected together a load of pre-written blocks.

[Altera_Forum]

you should take a look at DSP Builder Advanced Blockset 

 i've used Python (not myHDL) to generate VHDL. i used it mostly as a time saver, not to increase flexibility

[Altera_Forum]

I have used Python extensively for VHDL code generation. In addition, I have described a set of routines that make up a small declarative language. The Mako templating engine is excellent; it is the main tool used for automatic generation of entity, architecture, and configurable parameters that in VHDL are made as constants. 

 On top of this, the Qt GUI toolkit makes it easy to build applications with Python. I formerly used PyQt, but now Nokia has ported Qt to Python in the form of the module PySide, which has a freer license that PyQt.   James

[Altera_Forum]

thanks for the tip about PySide, i've used Qt in the past and really liked it

[Altera_Forum]

Hi All; 

 As a continuing thread to this discussion, I've provided a link to the video that I did last year on a PySide/Python GUI for automatic VHDL code generation. This GUI is built with Python and Qt/PySide. The only other python module used is Mako, where all the other functions are built with the standard library, such as regular expressions. However, another engineer and I put together a rapid application framework for building such GUI's, and we called it PyRad. The idea is that once a solid VHDL library or libraries modules are designed, then designing at the higher level with either a GUI or API based on python would allow for assembly of modules & rapid design. The programming paradigm is declarative.   p.s. There is a full screen button on the lower right of the video. Press this to see the GUI in the greatest detail.  http://www.viddler.com/explore/james_atlantix/videos/11/?secreturl=100698896     James

[Altera_Forum]

You may want to take a look at myhdl (http://www.myhdl.org/doku.php/start) 

It uses Python as the descriptive language and converts either to Verilog or VHDL.