Automating simulation for multiple data sets stored in RAM

[Altera_Forum]

I am currently trying to simulate my VHDL source with multiple data sets. What I am looking to do is compile with a specific MIF file to initialize my RAM to a specific data set, run simulation and then repeat until I have finished my tests. Is there any way to automate this process through scripting (TCL/Do/..?) in Altera 14.1 for Windows 64 bit? I can simulate one easily, but I have a rather large set of data to run through.

[Altera_Forum]

Yes, its possible to do what you want, but it depends on your design. You did not describe your code in detail, so its a bit hard to comment. Here's a few options; 

 1. Create a testbench for the device under test (DUT), and have your input/output data sets accessed via non-synthesizeable code, eg., something that looks like RAM to the DUT but is really some HDL that reads and writes files. This will be the fastest simulation solution.  2. Create a testbench for the DUT that includes input dual-port RAM and output dual-port RAM. The testbench accesses one port of the RAMs, while the DUT accesses the other. Your testbench code would need to read from file and write to input RAM, trigger the DUT to process the RAM data and write it to the output RAM, and then the testbench would read the output RAM and write it to file. This will take longer, but will look more like a hardware implementation.  3. Qsys system design with an Altera Avalon-MM BFM and dual-ported RAM components. The Qsys system would communicate with one port of the dual-port RAM, while the DUT connects to the other port. Using the Avalon-MM BFM you would write to the input RAM, then access a control register to trigger your DUT, then poll a status register until done, and then use the BFM to read the output RAM and write to a file  4. Qsys system with a JTAG to Avalon-MM bridge. Repeat 3, but this time in hardware and access the design using Tcl.  Which option sounds interesting to you?  Cheers, Dave

[Altera_Forum]

The first option seems the to be the most sensible.

[Altera_Forum]

--- Quote Start ---  The first option seems the to be the most sensible.  --- Quote End ---    Here's some VHDL example code that opens and reads files.  Its probably not what you want for your device, but you can copy the file access routines :)  Cheers, Dave