component input or output pin assignment

[Altera_Forum]

i have a component in my program (named fsm) that gives integers as outputs to another component (named pwm) which takes them as inputs. should i assign pins to these integers or that is done internally? if i should what pins should i assign? 

also anything std_logic or vector that is output from a component and input to another.

[Altera_Forum]

Hi, you can assign the pin location from QII software as following method: 

1. Assignment Editor 2. Pin Planner.  Else, you may also let the QII software auto fix the pin location for your design.

[Altera_Forum]

I suggest reading some basic VHDL info. Most books explain this http://www.alteraforum.com/forum/showthread.php?t=41998&highlight=books 

Also, if you search the internet using your favorite search engine, you should be able to find examples. The term you are looking for is "glue signal".  [edit] irish was just a little faster in answering, but I would like to reply to that as well, The question is about component mapping. You could do this trough pins and wires, but this is not how it is supposed to be, and it will make the sytsm unnecissary complex.

[Altera_Forum]

Hi Nada, 

 If I understand it correctly, you are just trying to connect instances created using FPGA core logic together but does not require any external signal coming out from the FPGA device. As mentioned by PietervanderStar, you could directly do the connection in VHDL or Verilog coding without going through any pin assignment. To add on, if you are using Quartus block diagram to create your design, you could just tie these ports using wires. Note that only those signals that you would like to export out from the FPGA device or import into FPGA from outside device require IO pin assignments. Hope this helps.