Avalon Bus Address alignment

[Altera_Forum]

Hi, 

I want to know how to use the Avalon Bus Address alignment feature. Is it automated by the Nios to choose the address alignment or do we have to manually do it ?

[Altera_Forum]

To answer the question you probably meant to ask: 

 32 bit memory accesses have to be aligned on 4 byte boundaries. There is no support for misaligned addresses.

[Altera_Forum]

The problem what I'm actually facing is I have control registers, which i access through Avalon Bus and perform read and write operations.  

Internally I have assigned register addresses as 0 1 2 3 4 5 etc. I'm facing problems trying to map the addresses sent by Avalon Bus to my internal register addresses.  I came across the document "Avalon Bus Specification Reference Manual" in which there is the concept of address alignment, Native address alignment in particular which solves my problem, but I'm not able to implement it.

[Altera_Forum]

Without byte enable the slave port uses native address alignment and following formula is used to calculate the address: 

 master address = slave base address + (slave word offset * master data width in bytes)

[Altera_Forum]

Thanks for the input. How do i derive slave address from Master address.?

[Altera_Forum]

Perhaps this helps... 

 32-Bit Master View of 16-Bit Slave Data:  32-bit Master Address Data with Native Alignment Data with Dynamic Bus Sizing BASE + 0x0 (word 0) 0×0000:OFFSET[0] OFFSET[1]:OFFSET[0] BASE + 0x4 (word 1) 0×0000:OFFSET[1] OFFSET[3]:OFFSET[2] BASE + 0x8 (word 2) 0×0000:OFFSET[2] OFFSET[5]:OFFSET[4] BASE + 0xC (word 3) 0×0000:OFFSET[3] OFFSET[7]:OFFSET[6] … ... ... BASE + 4N (word N) 0×0000:OFFSET[N] OFFSET[2N+1]:OFFSET[2N]    Where OFFSET corresponds to slave address.

[Altera_Forum]

Hi,  

I tried the above method but when master sends the address as BASE + 00 it corresponds to address "0" of the control register.. and when the master sends the address as BASE + 04 instead of corresponding to the address "1" I'm getting "4". What could be the reason for this. From what I understand the addresses sent by master are not under my control. It is supposed to understand the address alignment and send the address, but it is not happening. Help needed.

[Altera_Forum]

--- Quote Start ---  Hi,  I tried the above method but when master sends the address as BASE + 00 it corresponds to address "0" of the control register.. and when the master sends the address as BASE + 04 instead of corresponding to the address "1" I'm getting "4". What could be the reason for this. From what I understand the addresses sent by master are not under my control. It is supposed to understand the address alignment and send the address, but it is not happening. Help needed.  --- Quote End ---     Here are some of the things that I learnt recently...If you are using a tristate bridge then the slave has dynamic addressing...If not then you will have to check the component (edit component and check the deprecated settings) to figure out which alignment the component/slave has. Once you have determined that take a look at the attached document here. It explains how address[0] on FPGA should be connected to slave (page 97)

[Altera_Forum]

Could you please tell me how to check the address alignment in the component editor. i'm unable to find it.

[Altera_Forum]

i found out my design uses native address alignment.

[Altera_Forum]

In your SOPC system on the left hand side where your component is listed, do a right click on the component and select edit component...in interfaces you should see a check box to show deprecated settings...One thing to remember is that in the newer version everything is dynamic so you can assume you component is dynamic

[Altera_Forum]

By far the simplest solution is to convert your slave to be 32bit and just ignore the high bits and return zero when they are read. 

You should still check the relevant bytes enable(s) since 32 bit transfers from a 64bit master (eg PCIe) will be converted into 2 cycles - one of which will have no byte enables asserted.