Chip-planner block names inside the PLL

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Chip-planner block names inside the PLL

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What do these two blocks indicate in the chip-planner?

PLL DPA Output and PLL LVDS Output

Anybody know of a link to Altera's documentation on this kind of information related to the chip-planner? E.g. Arria V handbook says PLLs have 18 counters. How do I know which counter is 18th and which one is the first in the chip-planner? I am trying to add a location constraint to the counters for ALTLVDS instances in my design to work around an errata in the devices.

-sanjay

https://www.alteraforum.com/forum/attachment.php?attachmentid=7438

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