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Or to reframe my question :
Does Intel platform designer has any Hard IP which is equivalent to the Xilinx® UltraScale Devices Gen3 Integrated Block for PCIe® solution IP core ???
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Hi,
Thanks for using Intel community forum,
Kindly expect some delay in the reply due to holiday.
Thanks,
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Hi,
We do have a Design comparison with Xilinx User, please refer the link below.
What we would recommend based on the information that you provide at the moment will be Stratix and Agilex Family.
Those common PCIe IP such as AVST, AVMM , DMA and others are available inside Quartus.
For the other PCIe Design Example, you may refer to our FPGA Design Store.
Let me know if any further clarification is needed.
Regards,
Wincent_Intel
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Hi wchiah,
You didn't answer the question well ,
I want to use stratix10 fpga.
Question is :
Do we have any IP in platform generator that convert the Avalon Streaming Interface signals [ connected as as an pcie endpoint ] to the AXI4 Streaming interface signals ??
Or same question reframed as below
Does Intel platform designer has any Hard IP which is equivalent to the Xilinx® UltraScale Devices Gen3 Integrated Block for PCIe® solution IP core ???
-Piyush
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Hi Piyush,
Apologize for misunderstanding your question early on.
- Do we have any IP in platform generator that convert the Avalon Streaming Interface signals [ connected as a PCIe endpoint ] to the AXI4 Streaming interface signals ??
We have a function call Bursting Adaption, but as I see it is only applicable to AVMM
https://www.intel.com/content/www/us/en/docs/programmable/683609/21-3/burst-adaptation-to-axi.html - Does Intel platform designer has any Hard IP which is equivalent to the Xilinx® UltraScale Devices Gen3 Integrated Block for PCIe® solution IP core
Apologize that I not familiar with Xilinx product, but there is some comparison and recommended product with Xilinx UltraScale Device which is Intel Stratix 10 for example. Can I know which PCIe solution IP core you wish to compare with?
Most of common PCIe Hard/Soft IP such as AVST, AVMM , DMA and others are available in Intel product as well.
Let me know if the answer is still not clear.
Regards,
Wincent_C
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Hi Wincent_C,
Thanks for responding .
Question for 1st comment,
Is the function call Bursting Adaption that you pointed out is present as "AXI Bridge Intel FPGA IP" under Bridges and Adaptors section in Platform Designer ? Just wanted to confirm attaching the below snap.
Question for 2nd comment,
Below is the xilinx PCIe core interface snap which has the AXI4 ST interface with requestor and completion both. I need this type of PCIe core in our Altera Stratix10 FPGA. If that is not present I am trying to use avmm pcie bridge as endpoint + AXI bridge Intel IP with this I can reach till axi4. But my requirement is AXI4-ST, for that I initiated the request with IPS but they are not helping us.
Thanks again for your help and hoping to get some more support from experts.
Regards,
Piyush
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Hi Piyush,
- Is the function call Bursting Adaption that you pointed out is present as "AXI Bridge Intel FPGA IP" under Bridges and Adaptors section in Platform Designer? Just wanted to confirm attaching the below snap.
- My answer will be YES
- My answer will be YES
- Below is the xilinx PCIe core interface snap which has the AXI4 ST interface with requestor and completion both. I need this type of PCIe core in our Altera Stratix10 FPGA. If that is not present I am trying to use avmm pcie bridge as endpoint + AXI bridge Intel IP with this I can reach till axi4. But my requirement is AXI4-ST, for that I initiated the request with IPS but they are not helping us.
- For IPS, it only supports some funding projects, if the business case justifies that Intel PSG should invest in supporting the project, please contact the related contact listed in the IPS reply.
- I found one step-by-step solution on "Stratix 10 MX development kit HBM2 top and bottom example design with AXI-4 switch interface and system console accessible efficiency counters" .
https://community.intel.com/t5/FPGA-Wiki/Stratix-10-MX-development-kit-top-and-bottom-HBM2-AXI-4-switch/ta-p/1338339
Let me know if the answer is still not clear.
Regards,
Wincent_C
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Hi Wincent_C,
Thanks for confirming the bridge "AXI Bridge Intel FPGA IP".
- I found one step-by-step solution on "Stratix 10 MX development kit HBM2 top and bottom example design with AXI-4 switch interface and system console accessible efficiency counters" .
https://community.intel.com/t5/FPGA-Wiki/Stratix-10-MX-development-kit-top-and-bottom-HBM2-AXI-4-swi...
-> Please suggest, How will I get AXI4 to AXI4-Stream ? Is there any way to proceed ahead with the above link ?
-Regards
Piyush
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Hi,
Please suggest, How will I get AXI4 to AXI4-Stream ? Is there any way to proceed ahead with the above link ?
There is AXI-Bridge IP available , if you look in the Qsys. Can you try with the AXI-Bridge and let us know.
But there is no AXI streaming IP is available with us, But memory mapped solutions are available.
Regards,
Wincent_C
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What If I can write Verilog code to convert AXI4 to AXI4 stream, Is it possible to convert the AXI4 to AXI4 stream ?
I think this is last, I could do. I have the requirement to use AXI stream.
-
Regards
Piyush
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Hi,
If you confident to write verilog code to convert AXI4 to AXI4 Steam, feel free to try it.
However the conversation and other is out of my scope of support.
My suggestion for you is to reach out to PCIe IP engineering team for further consultation (as their responsibility to design the IP).
Hope this answer your question, Let me know if anything else I can help you.
Regards,
Wincent_C
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Hi wincent_C,
Please broadcast this Thread to community , If other member can help .
Thanks for your comments.
-Piyush
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Hi,
We do not receive any response from you to the previous answer that I have provided.
This thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get support from Intel experts.
Otherwise, the community users will continue to help you on this thread. Thank you
Regards,
Wincent_C
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Hi,
We do not receive any response from you to the previous answer that I have provided.
This thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get support from Intel experts.
Otherwise, the community users will continue to help you on this thread. Thank you
If you feel your support experience was less than a 9 or 10,
please allow me to correct it before closing or please let me know the cause so that I may improve your future support experience.
Regards,
Wincent_C

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