Hi,
I am working on implementation of cryptographic processors on Stratix and Stratix II. Actually I am generating a .vqm file from some external scripts and softwares in order to address the constraints required for crypto circut. The vqm is symantically correct qnd simulate correctly with Modelsim.
When I synthesize the whole design by linking the vqm netlist to a uart module (.vhd), a free 6502 (.vhd), other peripherals (.vhd), the quartus is able to synthesize is sucessfully with proper pin placement and work correctly on the board.
My problem is while connecting the vqm netlist to other modules, Quartus optimizes the netlist for some parameters. Specifically it changes some of the LUT_MASK which I described differently intially. This optimization does not affect the functionality but change the security constraint.
What I want is to synthesize the design in such a way that Quartus does not optimize the vqm netlist which I provide at all otherwise optimization on any other module is not a problem. Is there a way to achieve that.
Thanks in advance
Shivam
