Warning Messages in conjunction with for PLLs

[Altera_Forum]

Hello together, 

 for a new design i want to generate different clocks:  50 MHz intern 125 MHz intern 125 MHz extern 180° 87,5 MHz intern 66 MHz extern 64,167 MHz intern/extern  The input clock of the FPGA is 50 MHz.  The target device is an Altera Cyclone IV-E FPGA with four integrated PLLs.  PLL2: ------ in: 50 MHz (from extern) out0: 87,5 MHz intern out1: 50 MHz intern  PLL1: ----- in: 50 MHz intern out0: 125 MHz 180° extern out1: 125 MHz intern  PLL3: ----- in: 50 MHz intern out: 66 MHz extern  PLL4: ----- in: 50 MHz intern out:64,167 MHz intern/extern   At first I want to know if it is correct how I cascade the PLLs?   Is it actually necessary to generate an intern 50 MHZ clock for PLL1, PLL3, PLL4?  After compiling I get some kinds of warning messages:  Warning Message Type1: ------------------------ Warning: The parameters of the PLL PLL3:PLL3_inst|altpll:altpll_component|PLL3_altpll:auto_generated|pll1 and the PLL PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1 do not have the same values - hence these PLLs cannot be merged  Info: The values of the parameter "M" do not match for the PLL atoms PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1 and PLL PLL3:PLL3_inst|altpll:altpll_component|PLL3_altpll:auto_generated|pll1  Info: The value of the parameter "M" for the PLL atom PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1 is 77  Info: The value of the parameter "M" for the PLL atom PLL3:PLL3_inst|altpll:altpll_component|PLL3_altpll:auto_generated|pll1 is 33  Info: The values of the parameter "N" do not match for the PLL atoms PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1 and PLL PLL3:PLL3_inst|altpll:altpll_component|PLL3_altpll:auto_generated|pll1  Info: The value of the parameter "N" for the PLL atom PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1 is 6  Info: The value of the parameter "N" for the PLL atom PLL3:PLL3_inst|altpll:altpll_component|PLL3_altpll:auto_generated|pll1 is 5  Info: The values of the parameter "LOOP FILTER R" do not match for the PLL atoms PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1 and PLL PLL3:PLL3_inst|altpll:altpll_component|PLL3_altpll:auto_generated|pll1  Info: The value of the parameter "LOOP FILTER R" for the PLL atom PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1 is 12000  Info: The value of the parameter "LOOP FILTER R" for the PLL atom PLL3:PLL3_inst|altpll:altpll_component|PLL3_altpll:auto_generated|pll1 is 6000  Info: The values of the parameter "Min Lock Period" do not match for the PLL atoms PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1 and PLL PLL3:PLL3_inst|altpll:altpll_component|PLL3_altpll:auto_generated|pll1  Info: The value of the parameter "Min Lock Period" for the PLL atom PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1 is 19737  Info: The value of the parameter "Min Lock Period" for the PLL atom PLL3:PLL3_inst|altpll:altpll_component|PLL3_altpll:auto_generated|pll1 is 10150  Info: The values of the parameter "Max Lock Period" do not match for the PLL atoms PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1 and PLL PLL3:PLL3_inst|altpll:altpll_component|PLL3_altpll:auto_generated|pll1  Info: The value of the parameter "Max Lock Period" for the PLL atom PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1 is 30864  Info: The value of the parameter "Max Lock Period" for the PLL atom PLL3:PLL3_inst|altpll:altpll_component|PLL3_altpll:auto_generated|pll1 is 20408  Warning Message Type2: ------------------------ Warning: The input ports of the PLL PLL2:PLL2_inst|altpll:altpll_component|PLL2_altpll:auto_generated|pll1 and the PLL PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1 are mismatched, preventing the PLLs to be merged  Warning: PLL PLL2:PLL2_inst|altpll:altpll_component|PLL2_altpll:auto_generated|pll1 and PLL PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1 have different input signals for input port ARESET  Warning Message Type3: ------------------------ Warning: PLL "PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input  Info: Input port INCLK[0] of node "PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1" is driven by ClkCtrl:ClkCtrl_inst2|ClkCtrl_altclkctrl_7ji:ClkCtrl_altclkctrl_7ji_component|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node ClkCtrl:ClkCtrl_inst2|ClkCtrl_altclkctrl_7ji:ClkCtrl_altclkctrl_7ji_component|clkctrl1  Warning Message Type4: ------------------------ Warning: PLL "PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1" output port clk[0] feeds output pin "DviOClk~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance  Warning Message Type5: ------------------------ Warning: PLL "PLL3:PLL3_inst|altpll:altpll_component|PLL3_altpll:auto_generated|pll1" output port clk[0] feeds output pin "Clk_66_E6_0~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance  Could someone help me to solve the problems?  BR, Carsten

[Altera_Forum]

Hi cchabrie, 

 I received the same error after I turned on a number of synthesis options recommended to me by the Optimization Advisor.    I think the trigger for it may be one of these synthesis options:    Perform WYSIWYG Primitive Resyntheis=ON  Remove Redundant Logic Cells=ON  Perform Register Duplication for Performance=OFF   These were OFF, OFF, and On respectively in my design and when I changed them I got this warning.   I don't think this warning is a problem because I think it is telling you it is trying to merge logic functions between two PLLs, but found parameters with each PLL that prevented them from being merged. If the PLLs have different parameters we wouldn't want them merged anyway...right?   -Sean

[Altera_Forum]

What MegaFunctions or MegaCores are you implementing that are trying to merge PLLs? 

 True LVDS resources have PLL restrictions per side (Left / Right). Are you using the LVDS Serdes/DPA?

[Altera_Forum]

Hi Sean, 

 thank you for the hints. I don't want to merge PLLs. This is why I disable "Auto Merge PLLs" in the "Fitters Settings". With disabling this option, the are less warnings. But there are still two kinds of warnings:  Type 1: -------- Warning: PLL "PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1" input clock inclk[0] may have reduced jitter performance because it is fed by a non-dedicated input  Info: Input port INCLK[0] of node "PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1" is driven by ClkCtrl:ClkCtrl_inst2|ClkCtrl_altclkctrl_7ji:ClkCtrl_altclkctrl_7ji_component|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node ClkCtrl:ClkCtrl_inst2|ClkCtrl_altclkctrl_7ji:ClkCtrl_altclkctrl_7ji_component|clkctrl1  Type 2: ------- Warning: PLL "PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1" output port clk[0] feeds output pin "DviOClk~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance  Any ideas to remove this warnings??  Thank you  Br, Carsten  @fpgaGuy: I use the megafunction "ALTPLL".

[Altera_Forum]

Carsten, 

Without knowing more about the I/O IP and clocking architecture implementation it is difficult to say precisely what the issues are, but...   It looks to me like you have three issues:    1. Resource contention.    Two PLLs instantiated in the RTL are competing for the same resource in the silicon. This can happen with multiple ALTLVDS or transceivers when instances since there are dedicated clocks for them. Warning Message Type 1 makes this clear.  **Warning Message Type1: Warning: The parameters of the PLL [x] and the PLL [x] do not have the same values - hence these PLLs cannot be merged   2. Incorrect MegaFunction I/O connections.   Warning Messages of Type 2 indicate there are different sources (pins, registers, clock routing) for 2 separately instantiated PLL inputs.   **Warning Message Type2: Warning: The input ports of the PLL [A] and the PLL [B] are mismatched, preventing the PLLs to be merged   Warning: PLL [C] and PLL[D] have different input signals for input port ARESET  3. Using normal routing for clocks instead of dedicated clock routing.    This probably means the clock is passing through logic - it's not just connected to clock ports of PLLs, registers, RAMs, etc. That degrades performance and generally is not good design practice. Don't do this unless you REALLY must.  **Warning Message Type3: Warning: PLL [D] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input  **Warning Message Type4: Warning: PLL [E] output port clk[0] feeds output pin "DviOClk~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance  **Warning Message Type5: Warning: PLL [F] feeds output pin "Clk_66_E6_0~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance  Good luck, Mike  P.S. Have you tried using MySupport?

[Altera_Forum]

What are the interfaces or protocols at the I/O that are getting these warnings? 

 Please describe, preferably with a diagram, what your clocking architecture looks like. What is every element in the clocks' paths from pin, to PLL, to registers, RAMs, etc?

[Altera_Forum]

Hello fpgaGuy, 

 there is only one kind of error message left. An explanation follows at the end of this thread.  Warning: PLL "PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1" input clock inclk[0] may have reduced jitter performance because it is fed by a non-dedicated input  Info: Input port INCLK[0] of node "PLL4:PLL4_inst|altpll:altpll_component|PLL4_altpll:auto_generated|pll1" is driven by ClkCtrl:ClkCtrl_inst2|ClkCtrl_altclkctrl_7ji:ClkCtrl_altclkctrl_7ji_component|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node ClkCtrl:ClkCtrl_inst2|ClkCtrl_altclkctrl_7ji:ClkCtrl_altclkctrl_7ji_component|clkctrl1  explanation:  FPGA: Cyclone IV E - EP4CE115F23I7  Deticated Input Clock Pin of the FPGA: Pin A12 = CLK8  -- First PLL ------------- PLL2_inst : PLL2   PORT MAP (  areset => ResSys,  inclk0 => CLK, -- 50 MHz  c0 => Clk_50_E6_0_Pre, -- 50 MHz --> Clock Control Block  c1 => Clk_87_5_E6_0, -- 87,5 MHz  locked => PLL2_Locked  );  Clock Control Block ------------------ ClkCtrl_inst2 :   ClkCtrl PORT MAP ( inclk => Clk_50_E6_0_Pre,  outclk => Clk_50_E6_0  );  Second PLL ----------- PLL1_inst : PLL   PORT MAP (  areset => PLL2_Locked,  inclk0 => Clk_50_E6_0, -- 50MHz   c0 => Clk_125_E6_180, -- 125 MHz/ 180°  c1 => Clk_125_E6_0, -- 125 MHz/ 0°  locked => PLL1_Locked  );  Third PLL --------- PLL4_inst : PLL4  PORT MAP (  areset => PLL2_Locked,  inclk0 => Clk_50_E6_0, -- 50 MHz  c0 => Clk_64_166667_E6_0, -- 64,16667 MHz/ 0°  locked => PLL4_Locked  );   Any idea what`s the reason for the warning message?  BR,  Carsten

[Altera_Forum]

Hey, Carsten, 

That means the source of the PLL's input clock is from a sub-optimal location or primitive. I'd guess you have a transceiver or serdes reference clock connected to a sub-optimal pin. It could also be that you're trying to use a PLL output clock to feed a PLL that's meant to be fed directly from a dedicated reference clk pin, or at least a suitable, nearby dedicated clk input pin.