BJT Code needs Debugging

Altera_Forum · ‎02-18-2016

Hi, I'm trying to compile the attached source codes.

The NPN & PNP BJTs are in VHDL and the diode code is in verilog.

I am using Quartus.

Need help debugging.

Any help will be appreciated. :confused:

Altera_Forum · ‎02-20-2016

Did you try some of the online tools available on the web ?

Try searching for something like "verilog-to-vhdl-converter"

Altera_Forum · ‎02-20-2016

Actually I'm sure Quartus can compile both languages. My query is why the code shows errors when compiling.

I was asking for debugging help.

Thanks.

Altera_Forum · ‎02-22-2016

The 'electricalsystem' VHDL package is not synthesisable and there are function calls in the verilog without any definition of the function, not to mention the boundless real parameters declared. Quartus won't have any of that.

None of these modules are intended for use in an FPGA.

Cheers,

Alex

Altera_Forum · ‎02-22-2016

--- Quote Start ---

The 'electricalsystem' VHDL package is not synthesisable and there are function calls in the verilog without any definition of the function, not to mention the boundless real parameters declared. Quartus won't have any of that.

None of these modules are intended for use in an FPGA.

Cheers,

Alex

--- Quote End ---

Hi, thanks for the response. Can the attached jpeg vhdl source code for BJTs be used in FPGA?

Plus is there a tool that you know of that can input VHDL/verilog source code and output the algorithm implemented in equation form?

And a tool to convert VHDL/verilog to python?

Thanks.

Altera_Forum · ‎02-22-2016

That looks to be the same VHDL as you posted in your first post. No. The 'electricalsystem' VHDL package is not synthesisable.

I'm unaware of tools that do what you want.

Why on earth are you trying to put a BJT into an FPGA? This code will be to assist with a simulation.

Cheers,

Alex

Altera_Forum · ‎02-22-2016

--- Quote Start ---

That looks to be the same VHDL as you posted in your first post. No. The 'electricalsystem' VHDL package is not synthesisable.

I'm unaware of tools that do what you want.

Why on earth are you trying to put a BJT into an FPGA? This code will be to assist with a simulation.

Cheers,

Alex

--- Quote End ---

Ok. I get it now. Also I know verilog has pmos and nmos switches which are unidirectional which may serve my purposes. My question now is concerning my need for BJTs. I specifically wanted to use PNP because when the current through the gate is low and current in the collector is high, there is some current flow from the collector that passes through the gate. This characteristic is CRUCIAL for my design. Does the pmos primitives in verilog allow for this and if not, how do I configure the pmos so it does posses this characteristic?

Would you happen to know how to code for this?

Thanks.

Altera_Forum · ‎02-23-2016

The FPGA will only solve the logic part of your requirements - the logic only. If you specifically need the characteristics of a BJT then put a BJT down on your board!

You will not get any resources inside the FPGA to do this part of your puzzle.

Cheers,

Alex

Altera_Forum · ‎02-27-2016

--- Quote Start ---

The FPGA will only solve the logic part of your requirements - the logic only. If you specifically need the characteristics of a BJT then put a BJT down on your board!

You will not get any resources inside the FPGA to do this part of your puzzle.

Cheers,

Alex

--- Quote End ---

Hi, I wrote the attached source codes for pmos and nmos. I need help with the pmos for it to have the characteristics previously described. Any ideas?

Altera_Forum · ‎03-01-2016

This 'exercise' you're trying is not very practical. What's the goal here?

What you're trying to do with the nmos looks clear enough. The pmos should look near identical save the polarity of 'p_Gate'. i.e.

case p_Gate is
when '0' | 'L' => p_Out <= p_In;
when '1' | 'H' => p_Out <= 'Z';
when others => p_Out <= 'X';
end case;

However, these still can't (or perhaps "shouldn't") be use inside an FPGA - although you could consider using then if you connect 'p_Out' to a bidirectional pin on the FPGA. You should never tri-state signals internal to the FPGA - they're not designed to work in that way.

If you simply want an NMOS or PMOS FET, put one down. Save your FPGA for some logic!

Cheers,

Alex

Altera_Forum · ‎03-02-2016

Got it thanks. I suppose I have asked a lot of questions without properly explaining what I am working on which is why my approach seems a bit peculiar. I am attempting to implement a logic design from switch level since my architecture is hypothetically on a 3 dimensional scale and defining components on switch level would offer the best control (I believe) of the FPGAs performance. Thanks for the input.

Altera_Forum · ‎03-02-2016

An FPGA has a specified design - sets of slices with LUTs for the logic and registers. Writing code at the pmos/nmos level is not going to work because it will not map to an FPGA. Even in asic you would usually use an existing library rather than define your own - mainly because they are fully tested.

Your extreme low level approach is not going to work in an FPGA, and is unlikely to work in any ASIC tools either. Your code can be used for simulation and research purposes only...

Altera_Forum · ‎03-02-2016

Ok. Thanks. I'll switch to gate level and get in touch in case I encounter issues.