Timequest constraints for SRAM

[Altera_Forum]

Hello, 

I've got a board with Stratix V and Synchronous RAM on it. This is how my design looks like (see attachement)   First PLL is a Normal mode PLL that clocks desing logic. The second PLL has an external feedback an it is used to clock an external Synchronous SRAM. Length of feedback trace and Address/DQ traces are the same. This fact makes both clocks (RAM clock and internal one) phase aligned. My question is: How do I constraint (TimeQuest constraints) both Address and DQ outputs? (set_input_delay, set_output_delay). What clock should I use for constraining outputs/inputs to/from RAM? How do I "tell" TimeQuest about phase alignement mechanism?  Thank you, Alex

[Altera_Forum]

Study "timequest user guide (http://www.eet.bme.hu/~nagyg/mikroelektronika/timequest_user_guide.pdf)" or other tutorials. The mentioned document is one of the bests. 

you should create a virtual clock which is not connected to any port for set_input_delay and set_output_delay. Examples are available in the mentioned user guide. You could either create generated clocks manually or use the derive_pll_clocks command in your SDC.  Why do you use the feedback path in PLL?

[Altera_Forum]

--- Quote Start ---  Study "timequest user guide (http://www.eet.bme.hu/~nagyg/mikroelektronika/timequest_user_guide.pdf)" or other tutorials. The mentioned document is one of the bests. you should create a virtual clock which is not connected to any port for set_input_delay and set_output_delay. Examples are available in the mentioned user guide. You could either create generated clocks manually or use the derive_pll_clocks command in your SDC.  Why do you use the feedback path in PLL?  --- Quote End ---    Thank you for your reply. I've read all the documentation available at Altera web site. All the examples of source synchronous output interfaces send data outside of FPGA with clock that drives internal logic. In my case I use PLL with external feedback to clock RAM chip. There are many reasons of doing this: 1) I don't need to provide clock and data trace delays in my output/input constraints, because the phase skew is compensated by ext. feedback (ext. feedback trace length and Addr/Data trace length are the same) 2) If my board exposed to extreme cold or heat, so trace length are changed - external feedback always compensate these changes of my board traces. There are more. Like generic design etc.  My problem is - what clock do I pick for set_output_delay constraint. It cant be virtual one, but I also cant pick an internal clock, as it doesn't compensate last FF to pad path. (This internal clock never goes out) I cant pick a clock that goes out from PLL with external feedback (because I have to tell somehow to TimeQuest about clock relationships....)

[Altera_Forum]

Thank you for your answer,msj. 

I read all the documents availible at Altera web site and I didnt find any example that is similar to my design. All the SDR interface examples use a same clock for internal logic and for RAM clk pin. In my case, clock that drives an external RAM comes from PLL, and in terms of timequest it is a different clock. There are number of advantages in using ext. feedback PLL: 1) Phase alignement between clocks of internal logic and external chip 2)My board is exposed to extreme cold/heat. Trace length and conductivity changes in such conditions. External feedback alows to compensate these changes and keep the interface aligned.  I cannot use virtual clock for output delay constraint. I cannot use and internal clock, because PLL doesnt compensate a path from last FF to FPGA PAD (clock never leaves FPGA). I cannot use a clock from ext. fb. Pll because timequest doesnt see any relationship between this clock and data/address pins.

[Altera_Forum]

Virtual Clock is not a real physical clock; it is only a way to tell TimeQuest what IO requirements you have. So you could definitely define a virtual clock without a port associated to it. Study the user guide more thoroughly. There are lots of examples. None of them may be exactly what you need, but there are basics that you can modify. 

If a clock never leaves the FPGA, something is wrong with your design. Find the bug and correct it. Ensure it has not been optimized away. For set_input_delay & set_output_delay you need a virtual clock, not a real physical clock.