How to avoid negative slack?

[Altera_Forum]

Hi, 

 Currently i'm developing an SOPC also with some self developed components. I'm using QII-6.1 and the CyclonII-Nios-Eval board. Clock frequency is 85MHz. Looked fine so far, but during adding more components, i now get red marked Lines in the Compilation Report/Timing Analyzer, like e.g.  Clock Setup:'bla_nios:inst|pll_0:the_pll_0|altpll_0:the_pll:altpll:altpll_component|_clk2  If i click on it, it shows me a table with (also red marked) negative slack values, resulting in lower allowed clock frequencies.  I'm rather new in FPGA-programming, so i've not had that issue before. I assume, that i have too much load on a CLK signal - is that right?  Is there any chance to lower that load, e.g. by manually putting Buffers into the CLK signal? If so - which buffers (e.g. exp, global, lcell, row_global...)?  Or is the answer just: No, the Design is to complex to run with this CLK, the CLK frequency has to be lowered? :(  Any Information or pointers to literature would be welcome.  Cheers WK

[Altera_Forum]

If the clock is using global routing, it does not matter how many loads are on it. 

 Start with "Tools --> Advisors --> Timing Optimization Advisor --> Maximum Frequency (fmax)" in Quartus.  If none of the recommendations in the Advisor solve your problem, then refer to the Quartus handbook in Volume 2, Section III, Chapter 8 "Area and Timing Optimization".  If you still have timing violations after doing the basic things to improve fmax, then you might need to restructure your SOPC Builder system (for example, put some of the slaves on a bridge so that not everything is on one big Avalon bus).

[Altera_Forum]

The handbook is the best place to camp. As a quick note to check some timing assumptions - check the from and to clock to make sure this timing failure is in one clock domain. If those two clocks are different, then the way to get rid of that timing error is completely different. You can put in the appropriate clock domain crossing logic, or relax the timing constraints depending on how the design works. 

 The number of loads pulling down the time could come from the source signal, not the clock source. Take a look in Quartus help at maximum fanout, maxfan. There are settings you can change to start effecting this, such as optimization for speed. Assignments -> settings -> analysis & synthesis -> optimization technique -> speed.

[Altera_Forum]

Could the problem be that one of your components has a chunk of combinational logic which is causing an excessive delay between two registers. In this case adding a multicycle assignment in the right place could help. This has worked for me before.

[Altera_Forum]

--- Quote Start ---  In this case adding a multicycle assignment in the right place could help.  --- Quote End ---     Use a multicycle assignment only if you know it is valid for the design.  In FPGAs, multicycle assignments are typically used for a case like a divide-by-n clock enable where you can use a multicycle setup of n to give the destination register a window of n clock cycles to latch in new data.  There are some cases in FPGAs where you can use a multicycle setup to delay which clock edge at the destination register latches the new data, but you also must use a multicycle hold to check that the old data remains at the destination register input until that last clock period.  Randall asked whether the timing violation is for a path going between clock domains. The multicycle situation in my previous paragraph used to come up sometimes for paths that go between two PLL clock domains. There is a better solution now that eliminates some of those cross-domain violations. Turn on "Enable Clock Latency" in the "More timing Settings" dialog box.

[Altera_Forum]

Moin, 

 Thanks a lot for advice, looks like this "timing optimisation advicer" is exactly what i need.  I'm rather new to all this Advisors and Wizards and GUIs. In the past my life was much easier by using simple tools like vim, make and gcc :D :D   Cheers  WK

[Altera_Forum]

Hi, 

  I 'm using ALTERA fpga CYCLONE VI E. and working on Quartus 10.0 tool. when Enable the DMA in SOPC, after compilation Quartus showing worst case negative slack in "Time Quest Timing Analyzer" between DMA address BUS and Processor address BUS. How can i overcome this problem please suggest.   Please find the attachment regarding this.   Regards, Jayachandra.