Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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BUG ? QSYS version 13.1 quartus

Altera_Forum
Honored Contributor II
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Hi 

I have a problem with QSYS in Quartus II Version 13.1 

 

When i create my design in QSYS and then generate it. And then make my top file, and compile my design it gives my errors:12152. it refers my to: 

 

spipiggy : component LSA_version_2_spiCurrentDac 

timersupsolv3pump : component LSA_version_2_timerOutNdlWashPump 

uartusb : component LSA_version_2_uartEthernet 

 

The assigments of the componenents generated by qsys are not all correct. It seems it randomly connects components, i cant get this solved it does it every time i generate my qsys design. In SOPC build Version 9.1 i did not had this problem whit the same design. 

is this a BUG ?
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