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Altera_Forum
Honored Contributor I
830 Views

Basic question about Signals

Hi, I'm beginner in VHDL; 

 

My Question is ; when we define a signal as std_logic, but without any value. 

 

Is it same of saying that signal's starting value is '0' ?
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8 Replies
Altera_Forum
Honored Contributor I
46 Views

Hi, 

 

Yes in hardware it is either logic 0/1. 

But in simulation you can see uninitialized,unknown,Don't care etc 

example: signal I : integer range 0 to 3; -- I will initialise to 0 signal X : std_logic; -- X will initialise to 'U 

Also unused signal in design can be seen in simulation but not implemented in hardware. 

Go through Synthesizable and Nonsynthesizable vhdl design. 

 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
46 Views

Hi, 

 

In VHDL, you can define signals/variables using bit, bit_vector, std_logic & std_logic_vector. When you declare signals as bit/bit_vector, they can only take two values 0/1. When you use std_logic they can take 4 values 0/1/X/Z. When you only declare any signal / variable and do not initialize it , it does not have a value assigned to it and it defaults to X. So, after you declare a signal, you need to initialize it to a known value, either 0/1/Z.
Altera_Forum
Honored Contributor I
46 Views

 

--- Quote Start ---  

Hi, 

 

In VHDL, you can define signals/variables using bit, bit_vector, std_logic & std_logic_vector. When you declare signals as bit/bit_vector, they can only take two values 0/1. When you use std_logic they can take 4 values 0/1/X/Z. When you only declare any signal / variable and do not initialize it , it does not have a value assigned to it and it defaults to X. So, after you declare a signal, you need to initialize it to a known value, either 0/1/Z. 

--- Quote End ---  

 

 

This post is missing some values. If you take a look in the ieee.std_logic_1164 library you can see: 

type STD_ LOGIC is ( ‘U’, -- Uninitialized ‘X’, -- Forcing Unknown ‘0’, -- Forcing 0 ‘1’, -- Forcing 1 ‘Z’ -- High Impedance ‘W’, -- Weak Unknown ‘L’, -- Weak 0 ‘H’, -- Weak 1 ‘-’ -- don’t care );  

which give all the possible values. Using these will help you debug your design when simulating.  

In simulation std_logic initialises to u and in synthisization it depends on the tool. If you really want a '0', then initialise it to '0'.
Altera_Forum
Honored Contributor I
46 Views

 

--- Quote Start ---  

Hi, 

 

In VHDL, you can define signals/variables using bit, bit_vector, std_logic & std_logic_vector. When you declare signals as bit/bit_vector, they can only take two values 0/1. When you use std_logic they can take 4 values 0/1/X/Z. When you only declare any signal / variable and do not initialize it , it does not have a value assigned to it and it defaults to X. So, after you declare a signal, you need to initialize it to a known value, either 0/1/Z. 

--- Quote End ---  

 

 

In Verilog 4-state types have 0/1/X/Z, but VHDL std_ulogic has 9 states (std_logic is just a resolved version of std_ulogic, allowing multiple drivers) 

Also, in VHDL, all objects with no initial value default to their leftmost value, so for std_logic it is 'U', bit is '0', integer is -2^31 and so on. 

 

IMO, std_ulogic is preferable to bit as it will allow you see various issues because of things being assigned to 'U', and you can also assign odd or illegal combinations to 'X' (Unknown) or '-' (dont care) and see these flow through in simulation. 

 

By Default, Quartus (and most other compilers) will initialise registers to '0' where you have no initialisation. But memories will initialise to random noise when you havent set anything explicitly, so bare that in mind.
Altera_Forum
Honored Contributor I
46 Views

Thank you for your consideration, I got it and initialized all signals. On testbench wave, I was seeing 'U' at out. now it's fixed. But, At that time my CLK_50Mhz input defined in Entity started to be seen 'U' . Do I have to initialize 'CLK_50Mhz' in entity port as well? Please take a look on my basic code. 

 

entity son is port 

 

CLK_50MHz: in std_logic; 

myLED: out std_logic 

); 

end son; 

 

architecture behavior of son is 

 

signal counter:std_logic_vector(24 downto 0):="0000000000000000000000000"; 

signal CLK_1Hz:std_logic :='0'; 

begin 

--1011111010111100001000000 

 

prescaler: process(CLK_50MHz) 

begin 

if rising_edge(CLK_50MHz) then 

if counter<"1011111010111100001000000" then 

counter<=counter+1; 

else 

CLK_1Hz <= not CLK_1Hz; 

counter <= (others => '0'); 

end if;  

end if; 

end process prescaler; 

 

myLED<=CLK_1Hz; 

 

end behavior; 

 

That's a basic led blink, On testbench wave, getting CLK_50Mhz = 'U' and myLED = 0.  

 

and this's my testbench code( I don't post libraries here to keep the code short.) 

 

 

ENTITY testbench2 IS  

END ;  

 

ARCHITECTURE testbench2_arch OF testbench2 IS 

SIGNAL CLK_50MHz : STD_LOGIC ;  

SIGNAL myLED : STD_LOGIC ;  

COMPONENT son  

PORT (  

CLK_50MHz : in STD_LOGIC ;  

myLED : out STD_LOGIC );  

END COMPONENT ;  

BEGIN 

DUT : son  

PORT MAP (  

CLK_50MHz => CLK_50MHz , 

myLED => myLED ) ;  

 

 

 

-- "Clock Pattern" : dutyCycle = 50 

-- Start Time = 0 ps, End Time = 1 ns, Period = 100 ps 

clk_50mhz <= not clk_50mhz after 20 ns /2 ; 

 

 

-- "Constant Pattern" 

-- Start Time = 0 ps, End Time = 1 ns, Period = 0 ps 

Process 

Begin 

if myled /= ('0' ) then  

report " test case failed" severity error; end if; 

wait for 1 ns ; 

-- dumped values till 1 ns 

wait; 

End Process; 

END; 

 

 

THANKS AND BEST REGARDS
Altera_Forum
Honored Contributor I
46 Views

Thank you, Do I mind you to read my last post?

Altera_Forum
Honored Contributor I
46 Views

clk_50mhz <= not clk_50mhz after 20 ns /2 ; 

 

Here the clk starts and 'U', and the NOT of 'U' is also 'U'. So yes it needs to be initialised. 

 

There is a handy workaround so you can do it without initialisation, if you dont mind using a process (but it means you can add other handy stuff to the testbench): 

 

clk_gen_proc : process begin if clk /= '1' then clk <= '1'; else clk <= '0'; end if; wait for CLK_PERIOD/2; -- Timeout Control. Stops the testbench after G_TIMEOUT clocks without a "normal" finish if NOW >= G_TIMEOUT*CLK_PERIOD then report "Simulation ended due to TIMEOUT" severity FAILURE; wait; end if; end process;
Altera_Forum
Honored Contributor I
46 Views

thank you so much, it's done.

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