(vcom-1600) No feasible entries for subprogram

Altera_Forum · ‎02-09-2018

Dear Good people,

I was using following code while simulating it through modelsim, it shows following error : (vcom-1600) No feasible entries for subprogram "avalon_write". Can you guys please give me a solution? Thanks

Here is the code:

library IEEE;

library work;

library std;

library mm_master_bfm_0;

--library slave_0;

use std.textio.all;

use IEEE.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use IEEE.numeric_std.all;

use IEEE.math_real.all;

use work.all;

use mm_master_bfm_0.altera_avalon_mm_master_bfm_vhdl_p kg.all;

entity test_program_new is

generic

(

AV_ADDRESS_W : natural := 4;

AV_SYMBOL_W : natural := 8;

AV_NUMSYMBOLS : natural := 4;

AV_DATA_W : natural := 32;

--VERBOSITY : VERBOSITY_INFO;

INDEX_ZERO : natural := 0;

ADDR_MEM_CTRL : natural := 16;

ADDR_CASA_DUMMY : std_logic_vector (AV_ADDRESS_W -1 downto 0) := (others => '0'));

-- ADDR_MEM_CTRL_CONTROL_R : natural := (0*4);

-- ADDR_MEM_CTRL_PAYLOAD_ADDR_R : natural := (1*4);

-- ADDR_MEM_CTRL_CONFIG_ADDR_R : natural := (2*4);

-- ADDR_MEM_CTRL_CONFIG_ENTRY_NR_R : natural := (3*4);

-- ADDR_MEM_CTRL_PAYLOAD_SIZE_R : natural := (4*4);

-- ADDR_MEM_CTRL_ANC_PER_LINE_SIZE_R : natural := (5*4);

-- ADDR_MEM_CTRL_DID_SDID_R : natural := (6*4)

-- );

port (

clk : in std_logic ;

reset : in std_logic

);

end test_program_new;

architecture behave of test_program_new is

constant MAX_VHDL_BFM : integer := 1024;

signal api_if : std_logic_vector (MAX_VHDL_BFM - 1 downto 0);

--Master set and push

procedure master_set_and_push_command (request : in integer;

addr : in std_logic_vector (AV_ADDRESS_W -1 downto 0);

data : in std_logic_vector (AV_DATA_W -1 downto 0);

byte_enable : in std_logic_vector (AV_NUMSYMBOLS -1 downto 0);

idle : in integer;

init_latency : in integer;

signal api_if : inout mm_mstr_vhdl_if_t) is

variable bfm_id : integer := 0;

begin

set_command_request(request, bfm_id, api_if);

set_command_address(addr, bfm_id, api_if);

set_command_byte_enable(byte_enable, INDEX_ZERO, bfm_id, api_if);

set_command_idle(idle, INDEX_ZERO, bfm_id, api_if);

set_command_init_latency(init_latency, bfm_id, api_if);

set_command_burst_count(1, bfm_id, api_if);

set_command_burst_size(1, bfm_id, api_if);

if (request = REQ_WRITE) then

set_command_data(data, INDEX_ZERO, bfm_id, api_if);

push_command(bfm_id, api_if);

end if;

end procedure master_set_and_push_command;

--Master pop and get

procedure master_pop_and_get_response (

request : out integer;

addr : out std_logic_vector (AV_ADDRESS_W -1 downto 0);

data : out std_logic_vector (AV_DATA_W -1 downto 0);

signal api_if : inout mm_mstr_vhdl_if_t

) is

variable bfm_id : integer := 0;

begin

pop_response(bfm_id, api_if);

-- request <= get_response_request(request, bfm_id, api_if);

-- addr <= get_response_address(address, bfm_id, api_if);

-- data <= get_response_data(data, INDEX_ZERO, bfm_id, api_if);

get_response_request(request, bfm_id, api_if);

get_response_address(addr, bfm_id, api_if);

get_response_data(data, INDEX_ZERO, bfm_id, api_if);

end procedure master_pop_and_get_response;

--Avalon write

procedure avalon_write(

addr : in std_logic_vector (AV_ADDRESS_W-1 downto 0);

data : in std_logic_vector (AV_DATA_W -1 downto 0);

signal api_if : inout mm_mstr_vhdl_if_t

) is

variable bfm_id : integer := 0;

variable response_request:integer;

variable response_data : std_logic_vector (AV_DATA_W -1 downto 0);

variable response_addr : std_logic_vector (AV_ADDRESS_W -1 downto 0);

begin

master_set_and_push_command(REQ_WRITE,addr,data,"1 111",0,0,api_if);

-- wait until event_all_transactions_complete(bfm_id);

event_all_transactions_complete(bfm_id);

master_pop_and_get_response(response_request, response_addr, response_data, api_if);

if (response_request /= REQ_WRITE) then

report "Failure"

severity failure;

end if;

end procedure avalon_write;

--Checking the value

procedure check_value (

data_value : in std_logic_vector (31 downto 0);

ref_value : in std_logic_vector (31 downto 0)

) is

begin

if (data_value <= ref_value) then

report "PASS";

end if;

end procedure check_value;

--Checking the error

procedure check_error (

signal error : in integer) is

begin

report "error"

severity failure;

end procedure check_error;

--Avalon read

procedure avalon_read(

signal addr : in std_logic_vector (AV_ADDRESS_W-1 downto 0);

signal data : out std_logic_vector (AV_DATA_W -1 downto 0);

signal api_if : inout mm_mstr_vhdl_if_t

) is

variable bfm_id : integer := 0;

variable response_request:integer;

variable response_data : std_logic_vector (AV_DATA_W -1 downto 0);

variable response_addr : std_logic_vector (AV_ADDRESS_W -1 downto 0);

begin

master_set_and_push_command(REQ_READ,addr,x"000000 00","1111",0,0,api_if);

-- wait until signal_all_transactions_complete;

event_all_transactions_complete(bfm_id);

master_pop_and_get_response(response_request, response_addr , response_data, api_if );

if response_request /= REQ_READ then

report "Failure"

severity failure;

else

data <= response_data;

end if;

end procedure avalon_read;

begin

process(clk,reset)

begin

if rising_edge(clk) then

avalon_write(ADDR_CASA_DUMMY ,x"00000033", api_if); --SYNC2

avalon_write(ADDR_CASA_DUMMY ,x"00000011", api_if); --DA

avalon_write(ADDR_CASA_DUMMY ,x"00000005", api_if); --COUNT

avalon_write(ADDR_CASA_DUMMY ,x"00000001", api_if); --CMD

avalon_write(ADDR_CASA_DUMMY ,x"00000002", api_if);

avalon_write(ADDR_CASA_DUMMY ,x"00000003", api_if);

avalon_write(ADDR_CASA_DUMMY ,x"00000004", api_if);

avalon_write(ADDR_CASA_DUMMY ,x"00000005", api_if);

avalon_write(ADDR_CASA_DUMMY ,x"000000c1", api_if); --crc1

avalon_write(ADDR_CASA_DUMMY ,x"000000c2", api_if); --crc2

-- avalon_write(ADDR_CASA_DUMMY ,x"00000002", api_if); --wrong

-- avalon_write(ADDR_CASA_DUMMY ,x"00000003", api_if); --wrong

-- avalon_write(ADDR_CASA_DUMMY ,x"00000004", api_if); --wrong

-- avalon_write(ADDR_CASA_DUMMY ,x"000000fc", api_if); --SYNC1 (second packet)

-- avalon_write(ADDR_CASA_DUMMY ,x"00000033", api_if); --SYNC2

-- avalon_write(ADDR_CASA_DUMMY ,x"00000022", api_if); --DA

-- avalon_write(ADDR_CASA_DUMMY ,x"0000000a", api_if); --COUNT 10

-- avalon_write(ADDR_CASA_DUMMY ,x"00000001", api_if); --CMD

-- avalon_write(ADDR_CASA_DUMMY ,x"00000002", api_if);

-- avalon_write(ADDR_CASA_DUMMY ,x"00000003", api_if);

-- avalon_write(ADDR_CASA_DUMMY ,x"00000004", api_if);

-- avalon_write(ADDR_CASA_DUMMY ,x"00000005", api_if);

-- avalon_write(ADDR_CASA_DUMMY ,x"00000006", api_if);

-- avalon_write(ADDR_CASA_DUMMY ,x"00000007", api_if);

-- avalon_write(ADDR_CASA_DUMMY ,x"00000008", api_if);

-- avalon_write(ADDR_CASA_DUMMY ,x"00000009", api_if);

-- avalon_write(ADDR_CASA_DUMMY ,x"0000000a", api_if);

-- avalon_write(ADDR_CASA_DUMMY ,x"000000c1", api_if); --crc1

-- avalon_write(ADDR_CASA_DUMMY ,x"000000c2", api_if); --crc2

-- avalon_write(ADDR_CASA_DUMMY ,x"000000fb", api_if); --SYNC1 (third packet)

-- avalon_write(ADDR_CASA_DUMMY ,x"00000033", api_if); --SYNC2

-- avalon_write(ADDR_CASA_DUMMY ,x"00000011", api_if); --DA

-- avalon_write(ADDR_CASA_DUMMY ,x"00000005", api_if); --COUNT

-- avalon_write(ADDR_CASA_DUMMY ,x"00000001", api_if); --CMD

-- avalon_write(ADDR_CASA_DUMMY ,x"00000002", api_if);

-- avalon_write(ADDR_CASA_DUMMY ,x"00000003", api_if);

-- avalon_write(ADDR_CASA_DUMMY ,x"00000004", api_if);

-- avalon_write(ADDR_CASA_DUMMY ,x"00000005", api_if);

-- avalon_write(ADDR_CASA_DUMMY ,x"000000c1", api_if); --crc1

-- avalon_write(ADDR_CASA_DUMMY ,x"000000c2", api_if); --crc2

end process;

end architecture behave;

Altera_Forum · ‎02-12-2018

The api_if parameter in your avalon_write call is not the same types than the one in the procedure declaration. In the procedure declaration:

procedure avalon_write(
addr : in std_logic_vector (AV_ADDRESS_W-1 downto 0);
data : in std_logic_vector (AV_DATA_W -1 downto 0);
signal api_if : inout mm_mstr_vhdl_if_t
)

the api_if signal is of type mm_mstr_vhdl_if_t, but in your test bench you declared the api_if signal as a std_logic_vector:

signal api_if : std_logic_vector (MAX_VHDL_BFM - 1 downto 0);

Altera_Forum · ‎02-12-2018

This api_if signal has declaration of mm_mstr_vhdl_if_t which is below type:

type mm_mstr_vhdl_if_base_t is record

req : std_logic_vector (MM_MSTR_INIT downto 0);

ack : std_logic_vector (MM_MSTR_INIT downto 0);

data_in0 : integer;

data_in1 : integer;

data_in2 : std_logic_vector (MM_MAX_BIT_W - 1 downto 0);

data_out0 : integer;

data_out1 : integer;

data_out2 : std_logic_vector (MM_MAX_BIT_W - 1 downto 0);

events : std_logic_vector (MM_MSTR_EVENT_MIN_COMMAND_QUEUE_SIZE downto 0);

end record;

type mm_mstr_vhdl_if_t is array(MAX_VHDL_BFM - 1 downto 0) of mm_mstr_vhdl_if_base_t;

Can you suggest how to declare that in my test program? Thanks

Altera_Forum · ‎02-12-2018

simply:

signal api_if : mm_mstr_vhdl_if_t ;

Altera_Forum · ‎02-14-2018

Thank you very much.It works