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Best way to code a clock divider?

Altera_Forum
Honored Contributor II
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Hello, 

 

I have to divide a clock input signal by 2048. I was wondering which method was the best to implement this divider in a FPGA. I know that we can use either a counter or just some flip-flops along with some logic. 

 

Do you know what are the pros and cons of each method? 

 

I attached my source code. My design includes 9 flip-flops that produce a signal used to invert my output signal (my output clock). 

 

Thank you for your help. 

 

Best regards, 

 

Damien
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Altera_Forum
Honored Contributor II
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well I certainly wouldnt do it like that. 

The best way is to create a clock enable rather than an actual clock (so you clock the slow thing at the system clock rate, and only enable it once every 2048 clocks). Creating clocks from logic can create timing issues.
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Altera_Forum
Honored Contributor II
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What's the reason of manually synthesizing a counter, like you did? The logic synthesizer is supposed to do that boring job.  

In VHDL you can simply increment a 11bit count register and take the MSB. 

 

 

For example: 

entity divider is port (CLKIN : in std_logic; RESET : in std_logic; CLKOUT : out std_logic ); end entity divider; architecture divider_2048 of divider is signal cnt : unsigned(10 downto 0); begin process(RESET, CLK) begin if RESET = '1' then cnt <= (others => '0'); elsif rising_edge(CLK) then cnt <= cnt + 1; end if; end process; Q <= cnt(10); end architecture divider_2048;
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

What's the reason of manually synthesizing a counter, like you did? The logic synthesizer is supposed to do that boring job.  

--- Quote End ---  

 

 

School assignment most likely. :D
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Altera_Forum
Honored Contributor II
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Thank you very much, 

 

Only one small process to do the job, wonderful!
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Altera_Forum
Honored Contributor II
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There are some errors in that code (inconsistent port names). Here is a corrected version: 

 

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; entity divider is port (CLKIN : in std_logic; RESET : in std_logic; CLKOUT : out std_logic ); end entity divider; architecture divider_2048 of divider is signal cnt : unsigned(10 downto 0); begin process(RESET, CLKIN) begin if RESET = '1' then cnt <= (others => '0'); elsif rising_edge(CLKIN) then cnt <= cnt + 1; end if; end process; CLKOUT <= cnt(10); end architecture divider_2048;
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