help for vhdl processing image

[Altera_Forum]

Hi, 

I m new with vhdl, I have an image processing application to describe it with vhdl code, this application, is based on many mathematical function like, convolution, Gaussian filter, integration and other, witch must be applied on bmp image 640*640 pixels. for the original code (c) we used for loop to sweep all pixels, many types like real, float.... and we have a sequential algorithm...  but for the vhdl description I don't know really if I have to do the some or to use memory (for loop), and if I use memories how can I read or write every element?? what is the best to use function module for every c function or to replace it with entity and architecture ?? please if there is any one how is working with vhdl image processing to advice me how to have first step and thanks :) cordially

[Altera_Forum]

C image processing can't be simply copied to VHDL, it has to be basically redesigned. Available FPGA resources suggest a sequential processing of image data stored in FPGA internal or more likely external RAM. Sequential processing involves state machines and sequence controllers, not for loops. HDL iteration schemes are describing parallel processing and tend to make FPGA resource utilization "explode" for large data structures.

[Altera_Forum]

thanks FvM for your information,but for example, when I have to first to stock image in the ram, second read cases of this ram, third modify this pixel finally to write it in an other place of ram, how to access for the cases of the ram if i can't use for loop,how to paralleled the code if it is sequential, I know that is using FSM but it still sequential, can you clear more really I need every advice and idea to achieve my project and really I will be thankful.

[Altera_Forum]

RAM access is one location per read/write, e.g. per clock cycle for a synchronous RAM. The exact RAM access sequence depends on the intended image processing operation. It will be rather complex of image data of adjacent pixels have to be considered. For a simple per pixel manipulation (contrast, brightness, color saturation), you'll just step sequentially through all pixel addresses.

[Altera_Forum]

As FvM wrote, you try to process one pixel per clock and the RAM access sequence can get very complicated depending on the amount of data you need to reference to produce an output pixel. As part of the Video and Image Processing Suite of IP, Altera supplies a 2-D FIR Filter which may be useful to you. You may find the book "Design for Embedded Image Processing on FPGAs" by Donald G Bailey useful. Chapter 8 Local Filters covers this particular topic pretty well.