Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
882 Views

Bi Directional pins

Hello all I am trying to utilize bi-directional ports of the inout type for the first time. 

 

I found the following code on the Altera website. 

https://www.altera.com/support/support-resources/design-examples/design-software/vhdl/v_bidir.html 

 

 

 

However, I am not able to simulate this code. No matter how I try to operate the code the inout port, "bidir" in this case, is always undefined "UUUUUUUU" 

 

Has anyone used this code successfully?  

 

Thanks!
0 Kudos
10 Replies
Altera_Forum
Honored Contributor I
38 Views

You don't drive the entity correctly. Show your test bench. 

 

Notice that the register signals a and b are uninitialized in the simulation. In real hardware, they are usually cleared by power-on-reset. Adding initializer expressions for the signals would better correspond to hardware behavior.
Altera_Forum
Honored Contributor I
38 Views

Here is the testbench. I updated it to add initial condition for the inp and outp signals, but it still does not work. 

In this code I was only trying to send a signal to the inp and have it appear on the bidir. 

 

Thanks for your help! 

 

 

library ieee;  

use IEEE.STD_LOGIC_1164.ALL, ieee.numeric_std.all; 

 

 

entity bidir_test is 

end entity bidir_test; 

 

architecture verify of bidir_test is 

 

component bidir 

PORT( 

bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); 

oe, clk : IN STD_LOGIC; 

inp : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 

outp : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); 

end component; 

 

constant clk_period : time := 1 us;-- 1Mhz clock 

signal clk, oe: std_logic; 

signal inp, outp: std_logic_vector (7 downto 0):= "00000000"; 

signal bidir1: std_logic_vector (7 downto 0):= "ZZZZZZZZ"; 

 

 

 

begin 

uut: bidir Port Map (bidir => bidir1, inp => inp, outp => outp, oe => oe, clk => clk); 

clk_process: process 

begin 

clk <= '0'; 

wait for clk_period/2; --for 0.5 ns signal is '0'. 

clk <= '1'; 

wait for clk_period/2; --for next 0.5 ns signal is '1'. 

end process; 

 

 

 

test_case: process is 

begin 

 

wait for 500 ns; 

 

oe <= '1'; 

bidir1 <= "ZZZZZZZZ"; 

inp <= "11111111"; 

 

 

wait for 1000 ns; 

 

oe <= '1'; 

bidir1 <= "ZZZZZZZZ"; 

inp <= "11111111"; 

 

 

wait for 1000 ns; 

 

oe <= '1'; 

bidir1 <= "ZZZZZZZZ"; 

inp <= "00000000"; 

 

wait for 1000 ns; 

 

oe <= '1'; 

bidir1 <= "ZZZZZZZZ"; 

inp <= "00000000"; 

 

end process test_case; 

end architecture verify;
Altera_Forum
Honored Contributor I
38 Views

you are driving bidir with Z and also enabling the tristate to pass input. That is not right.

Altera_Forum
Honored Contributor I
38 Views

I tried it without driving bidir at all and it still does not work. 

 

Any other suggestions are greatly appreciated. 

 

Thanks
Altera_Forum
Honored Contributor I
38 Views

I note your clock is 1 us period but your waits are 500 then 1000 or so ns. You may run into sampling troubles (delta delay etc.) 

also check that lower module is indeed found &bound
Altera_Forum
Honored Contributor I
38 Views

Thanks Kaz I don't think its a sampling problem. For example the inp to a register and outp to b register all works fine. 

The birdir just does not ever show anything other than undefined. Do you see any issues with how the testbench is driving the bibir line through inp?
Altera_Forum
Honored Contributor I
38 Views

 

--- Quote Start ---  

Thanks Kaz I don't think its a sampling problem. For example the inp to a register and outp to b register all works fine. 

The birdir just does not ever show anything other than undefined. Do you see any issues with how the testbench is driving the bibir line through inp? 

--- Quote End ---  

 

 

It seems that example model is wrong. 

look t my changes: 

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY bidir IS PORT( bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); oe, clk : IN STD_LOGIC; inp : IN STD_LOGIC_VECTOR (7 DOWNTO 0); outp : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END bidir; ARCHITECTURE maxpld OF bidir IS SIGNAL a : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores -- value from input. SIGNAL b : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores BEGIN -- feedback value. PROCESS(clk) BEGIN IF clk = '1' AND clk'EVENT THEN -- Creates the flipflops a <= inp; outp <= b; END IF; END PROCESS; PROCESS (oe,a,b,bidir) -- Behavioral representation BEGIN -- of tri-states. IF( oe = '0') THEN bidir <= "ZZZZZZZZ"; b <= bidir; ELSE bidir <= b; b <= a; END IF; END PROCESS; END maxpld;
Altera_Forum
Honored Contributor I
38 Views

Thanks Kaz, looks like you changed the sensitivity list for the second process.  

I'll try it out.
Altera_Forum
Honored Contributor I
38 Views

There is more changes than just sensitivity list. see assignment when oe is not zero

Altera_Forum
Honored Contributor I
38 Views

Kaz, I wanted to follow up. Your code changes work perfectly and have been verified in hardware. 

 

Thanks so much for your help. Is there someone we can contact to update the web page with your changes?
Reply