Bit widths for addition

[Altera_Forum]

Hi, I am trying to write a pipelined adder for a filter design. all the gaussianPixels are 8 bits wide. 

 gaussianPartialSum0 <= ("00" & gaussianPixels(0)) + ('0' & gaussianPixels(3) & '0') + ("00" & gaussianPixels(6));  gaussianPartialSum1 <= ('0' & gaussianPixels(1) & '0') + (gaussianPixels(4) & "00" ) + ('0' & gaussianPixels(7) & '0');  gaussianPartialSum2 <= ("00" & gaussianPixels(2)) + ('0' & gaussianPixels(5) & '0') + ("00" & gaussianPixels(8));    Gaussian_data_out <= std_logic_vector(gaussianPartialSum0 + gaussianPartialSum1 + gaussianPartialSum2);  doing hand calculation, i see that gPS0 and gPS2 should be 10 bits wide and gPS1 should be 11 bits wide. But when i try to make them this length, vhdl complains that the bit widths dont match. The error is that the expression for gPS1 evaluates to 10 bits instead of 11.   I'm not familiar with the rules of how VHDL calculates the required bit widths for addition. so by leaving all the gPS signals to 10 bits, im getting the incorrect answer. Is there something else I can do to get the correct values?

[Altera_Forum]

In VHDL, the width of the result is as wide as the largest vector in the sum. 

So 4bits + 2 bits + 2 bits + 1bit = 4 bit result.  If you need more, just add more bits to the largest operand

[Altera_Forum]

--- Quote Start ---  In VHDL, the width of the result is as wide as the largest vector in the sum. So 4bits + 2 bits + 2 bits + 1bit = 4 bit result.  If you need more, just add more bits to the largest operand  --- Quote End ---    So in my case those would be the operands to the '+' operator? So in this case, can i just append another zero to the MSB of the gaussianPixel signals so that they are seen by the '+' operator as wider signals?   so instead of adding (2+8) + (1+8+1) + (2+8) can I make it (3+8) + (2+8+1) + (3+8) to get the 11 bits i need?

[Altera_Forum]

Yes - that should work. 

the numeric_std has a resize function that will get the correct size for you (though not append bits at the LSB) and if using the signed type, will sign extend the value.

[Altera_Forum]

--- Quote Start ---  Yes - that should work. the numeric_std has a resize function that will get the correct size for you (though not append bits at the LSB) and if using the signed type, will sign extend the value.  --- Quote End ---    Ok. thank you. I will try that. These values are all unsigned so hopefully it wont do any bit extension or anything.

[Altera_Forum]

--- Quote Start ---  Ok. thank you. I will try that. These values are all unsigned so hopefully it wont do any bit extension or anything.  --- Quote End ---    Look at the code that implements the resize() function in the numeric_std source.   Please note that it works on only unsigned and signed types, not std_logic_vectors.  For unsigned operands, it boils down to simple zero extension. For signed operands, it does proper sign extension.