Building a composed component with a instance that has a SYSTEM_INFO parameter

[SimonT]

I have an integrated circuit connected to the FPGA. The circuit has an SPI interface and various other interfaces. For portablity of my HDL and SW code I want to use platform designer and build a composed component with a SW driver to control the device in various applications.

For initial testing I startet with a simple _hw.tcl file wich includes only the SPI master and exports all it's interfaces.

package require -exact qsys 16.1
set_module_property name my_composed_component
set_module_property COMPOSITION_CALLBACK composed_component

proc composed_component {} {

# Instances
add_instance spiInstance altera_avalon_spi
# add_instance myComponent_A; To be added later
# add_instance myComponent_B; To be added later

# Interfaces
add_interface clk clock end
add_interface reset reset end
add_interface spi_control_port avalon slave
add_interface spi_irq interrupt end
add_interface external conduit end

# Connections
set_interface_property clk EXPORT_OF spiInstance.clk
set_interface_property reset EXPORT_OF spiInstance.reset
set_interface_property spi_control_port EXPORT_OF spiInstance.spi_control_port
set_interface_property spi_irq EXPORT_OF spiInstance.irq
set_interface_property external EXPORT_OF spiInstance.external

}

Including the component in Platform designer works perfectly fine, but I am not able to generate the HDL code. During generation the following errors pop up.

Info: spiInstance: Starting RTL generation for module 'niosv_my_composed_component_0_spiInstance'
Info: spiInstance:   Generation command is [exec /home/simon/intelFPGA_lite/23.1std/quartus/linux64/perl/bin/perl -I /home/simon/intelFPGA_lite/23.1std/quartus/linux64/perl/lib -I /home/simon/intelFPGA_lite/23.1std/quartus/sopc_builder/bin/europa -I /home/simon/intelFPGA_lite/23.1std/quartus/sopc_builder/bin -I /home/simon/intelFPGA_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I /home/simon/intelFPGA_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi -- /home/simon/intelFPGA_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi/generate_rtl.pl --name=niosv_my_composed_component_0_spiInstance --dir=/tmp/alt0333_2429507840219227742.dir/0008_spiInstance_gen/ --quartus_dir=/home/simon/intelFPGA_lite/23.1std/quartus --verilog --config=/tmp/alt0333_2429507840219227742.dir/0008_spiInstance_gen//niosv_my_composed_component_0_spiInstance_component_configuration.pl  --do_build_sim=0  ]
Info: spiInstance: Illegal division by zero at /home/simon/intelFPGA_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi/em_spi_qsys.pm line 330.
Info: spiInstance: Done RTL generation for module 'niosv_my_composed_component_0_spiInstance'
Error: spiInstance: Failed to find module niosv_my_composed_component_0_spiInstance
Info: spiInstance: "my_composed_component_0" instantiated altera_avalon_spi "spiInstance"
Error: Generation stopped, 108 or more modules remaining
Info: niosv: Done "niosv" with 40 modules, 16 files
Error: qsys-generate failed with exit code 1: 2 Errors, 3 Warnings

I think the problem that the spi instance is not found results from

Info: spiInstance: Illegal division by zero at /home/simon/intelFPGA_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi/em_spi_qsys.pm line 330.

I have checked the content of the PM file. In line 330 the following code is executed

my $ss_delay_quantum = $CLOCKDIV / $clock_freq / 2; 

The clock frequency is a SYSTEM_INFO based parameter

add_parameter inputClockRate LONG
set_parameter_property inputClockRate DEFAULT_VALUE {0}
set_parameter_property inputClockRate DISPLAY_NAME {inputClockRate}
set_parameter_property inputClockRate VISIBLE {0}
set_parameter_property inputClockRate AFFECTS_GENERATION {1}
set_parameter_property inputClockRate HDL_PARAMETER {0}
set_parameter_property inputClockRate SYSTEM_INFO {clock_rate clk}
set_parameter_property inputClockRate SYSTEM_INFO_TYPE {CLOCK_RATE}
set_parameter_property inputClockRate SYSTEM_INFO_ARG {clk}

It seems that the clock frequency is not set correct and remains at it's default value 0.

After a bit of research I have found another ticket with a very similar issue. Also in this case there is an issue with a component instance that makes use of a SYSTEM_INFO parameter.

https://community.intel.com/t5/Intel-Quartus-Prime-Software/How-to-get-QSYS-to-propagate-SYSTEM-INFO-GENERATION-ID-value/m-p/1365929

I think that the issue I am observing here is a bug. It seems that it is simply impossible to use component instances that relay on SYSTEM_INFO parameters within a composed component.

Is there any way to use instances with SYSTEM_INFO parameter within a composed component?

If not, is there any other method to create a custom component that includes multiple component instances and can be linked to a single _sw.tcl driver?

Version Information: Quartus Prime Lite 23.1