Building a composed component with a instance that has a SYSTEM_INFO parameter

SimonT · ‎09-02-2025

I have an integrated circuit connected to the FPGA. The circuit has an SPI interface and various other interfaces. For portablity of my HDL and SW code I want to use platform designer and build a composed component with a SW driver to control the device in various applications.

For initial testing I startet with a simple _hw.tcl file wich includes only the SPI master and exports all it's interfaces.

package require -exact qsys 16.1
set_module_property name my_composed_component
set_module_property COMPOSITION_CALLBACK composed_component

proc composed_component {} {

# Instances
add_instance spiInstance altera_avalon_spi
# add_instance myComponent_A; To be added later
# add_instance myComponent_B; To be added later

# Interfaces
add_interface clk clock end
add_interface reset reset end
add_interface spi_control_port avalon slave
add_interface spi_irq interrupt end
add_interface external conduit end

# Connections
set_interface_property clk EXPORT_OF spiInstance.clk
set_interface_property reset EXPORT_OF spiInstance.reset
set_interface_property spi_control_port EXPORT_OF spiInstance.spi_control_port
set_interface_property spi_irq EXPORT_OF spiInstance.irq
set_interface_property external EXPORT_OF spiInstance.external

}

Including the component in Platform designer works perfectly fine, but I am not able to generate the HDL code. During generation the following errors pop up.

Info: spiInstance: Starting RTL generation for module 'niosv_my_composed_component_0_spiInstance'
Info: spiInstance:   Generation command is [exec /home/simon/intelFPGA_lite/23.1std/quartus/linux64/perl/bin/perl -I /home/simon/intelFPGA_lite/23.1std/quartus/linux64/perl/lib -I /home/simon/intelFPGA_lite/23.1std/quartus/sopc_builder/bin/europa -I /home/simon/intelFPGA_lite/23.1std/quartus/sopc_builder/bin -I /home/simon/intelFPGA_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I /home/simon/intelFPGA_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi -- /home/simon/intelFPGA_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi/generate_rtl.pl --name=niosv_my_composed_component_0_spiInstance --dir=/tmp/alt0333_2429507840219227742.dir/0008_spiInstance_gen/ --quartus_dir=/home/simon/intelFPGA_lite/23.1std/quartus --verilog --config=/tmp/alt0333_2429507840219227742.dir/0008_spiInstance_gen//niosv_my_composed_component_0_spiInstance_component_configuration.pl  --do_build_sim=0  ]
Info: spiInstance: Illegal division by zero at /home/simon/intelFPGA_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi/em_spi_qsys.pm line 330.
Info: spiInstance: Done RTL generation for module 'niosv_my_composed_component_0_spiInstance'
Error: spiInstance: Failed to find module niosv_my_composed_component_0_spiInstance
Info: spiInstance: "my_composed_component_0" instantiated altera_avalon_spi "spiInstance"
Error: Generation stopped, 108 or more modules remaining
Info: niosv: Done "niosv" with 40 modules, 16 files
Error: qsys-generate failed with exit code 1: 2 Errors, 3 Warnings

I think the problem that the spi instance is not found results from

Info: spiInstance: Illegal division by zero at /home/simon/intelFPGA_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi/em_spi_qsys.pm line 330.

I have checked the content of the PM file. In line 330 the following code is executed

my $ss_delay_quantum = $CLOCKDIV / $clock_freq / 2;

The clock frequency is a SYSTEM_INFO based parameter

add_parameter inputClockRate LONG
set_parameter_property inputClockRate DEFAULT_VALUE {0}
set_parameter_property inputClockRate DISPLAY_NAME {inputClockRate}
set_parameter_property inputClockRate VISIBLE {0}
set_parameter_property inputClockRate AFFECTS_GENERATION {1}
set_parameter_property inputClockRate HDL_PARAMETER {0}
set_parameter_property inputClockRate SYSTEM_INFO {clock_rate clk}
set_parameter_property inputClockRate SYSTEM_INFO_TYPE {CLOCK_RATE}
set_parameter_property inputClockRate SYSTEM_INFO_ARG {clk}

It seems that the clock frequency is not set correct and remains at it's default value 0.

After a bit of research I have found another ticket with a very similar issue. Also in this case there is an issue with a component instance that makes use of a SYSTEM_INFO parameter.

https://community.intel.com/t5/Intel-Quartus-Prime-Software/How-to-get-QSYS-to-propagate-SYSTEM-INFO-GENERATION-ID-value/m-p/1365929

I think that the issue I am observing here is a bug. It seems that it is simply impossible to use component instances that relay on SYSTEM_INFO parameters within a composed component.

Is there any way to use instances with SYSTEM_INFO parameter within a composed component?

If not, is there any other method to create a custom component that includes multiple component instances and can be linked to a single _sw.tcl driver?

Version Information: Quartus Prime Lite 23.1

RichardTanSY_Altera · ‎09-04-2025

I think I almost understand what you're trying to do here. The component you're attempting to add is the SPI (4-Wire Serial) Altera FPGA IP (altera_avalon_spi). With the usual flow by adding the component manually into the system, the Platform Designer (PD) is able to generate the HDL successfully.

I added the SPI (4-Wire Serial) Altera FPGA IP component, resolved any errors as needed, and then went to File > Export System as .tcl Component. PD will generated a _hw.tcl file.

If you cross-check the _hw.tcl, you'll notice that there are parameter values set in the _hw.tcl, which I suspect are missing in your current my_composed_component —and that’s likely what causes the error message during your composed_component HDL generation.

Regards,

Richard Tan

# _hw.tcl file for test
package require -exact qsys 14.0

# module properties
set_module_property NAME {test_export}
set_module_property DISPLAY_NAME {test_export_display}

# default module properties
set_module_property VERSION {1.0}
set_module_property GROUP {default group}
set_module_property DESCRIPTION {default description}
set_module_property AUTHOR {author}

set_module_property COMPOSITION_CALLBACK compose
set_module_property opaque_address_map false

proc compose { } {
# Instances and instance parameters
# (disabled instances are intentionally culled)
add_instance clk_0 clock_source 24.1
set_instance_parameter_value clk_0 {clockFrequency} {50000000.0}
set_instance_parameter_value clk_0 {clockFrequencyKnown} {1}
set_instance_parameter_value clk_0 {resetSynchronousEdges} {NONE}

add_instance spi_0 altera_avalon_spi 24.1
set_instance_parameter_value spi_0 {clockPhase} {0}
set_instance_parameter_value spi_0 {clockPolarity} {0}
set_instance_parameter_value spi_0 {dataWidth} {8}
set_instance_parameter_value spi_0 {disableAvalonFlowControl} {0}
set_instance_parameter_value spi_0 {insertDelayBetweenSlaveSelectAndSClk} {0}
set_instance_parameter_value spi_0 {insertSync} {0}
set_instance_parameter_value spi_0 {lsbOrderedFirst} {0}
set_instance_parameter_value spi_0 {masterSPI} {1}
set_instance_parameter_value spi_0 {numberOfSlaves} {1}
set_instance_parameter_value spi_0 {syncRegDepth} {2}
set_instance_parameter_value spi_0 {targetClockRate} {128000.0}
set_instance_parameter_value spi_0 {targetSlaveSelectToSClkDelay} {0.0}

# connections and connection parameters
add_connection clk_0.clk spi_0.clk clock

add_connection clk_0.clk_reset spi_0.reset reset

# exported interfaces
add_interface clk clock sink
set_interface_property clk EXPORT_OF clk_0.clk_in
add_interface reset reset sink
set_interface_property reset EXPORT_OF clk_0.clk_in_reset
add_interface spi_0_external conduit end
set_interface_property spi_0_external EXPORT_OF spi_0.external
add_interface spi_0_irq interrupt sender
set_interface_property spi_0_irq EXPORT_OF spi_0.irq
add_interface spi_0_spi_control_port avalon slave
set_interface_property spi_0_spi_control_port EXPORT_OF spi_0.spi_control_port

# interconnect requirements
set_interconnect_requirement {$system} {qsys_mm.clockCrossingAdapter} {HANDSHAKE}
set_interconnect_requirement {$system} {qsys_mm.enableEccProtection} {FALSE}
set_interconnect_requirement {$system} {qsys_mm.insertDefaultSlave} {FALSE}
set_interconnect_requirement {$system} {qsys_mm.maxAdditionalLatency} {1}
}

SimonT · ‎09-04-2025

Thanks Richard.

I did not knew that it is possible to create the _hw.tcl directly from platform designer. That is brilliant and simplify things a lot.
I have now successfully created a composed with one altera_avalon_spi and 2 altera_avalon_pio instances and called it myCircuit_hw.tcl
Additionally I have created a myCircuit_sw.tcl for the component.

The component is integrated in a parent qsys file with niosv processor and compiles.

When I generate the BSP the, BSP editor shows three Modules, but not the driver defined in the myCircuit_sw.tcl
All three modules have some dependecy. Therefore I want to not only link them in HW, but also have a single SW driver, that handles the communication with the SPI and both PIOs.

RichardTanSY_Altera · ‎09-04-2025

It seems like you're having trouble with getting the required result using the BSP Editor.

Unfortunately, the BSP Editor is not within my area of expertise. Would you mind posting a new question in the Embedded Design Suite category on the Intel Community forum?
https://community.intel.com/t5/Nios-V-II-Embedded-Design-Suite/bd-p/nios-II-embedded-design-suite

The experts there will be able to assist you with your follow-up questions and issues.

Let me know if you have further question related to Platform Designer.

Regards,
Richard Tan