Bus Problems With BDF files

[Altera_Forum]

I'm working on a project that I almost had done about four months ago, but then I had an accident that kept me from working. I'm getting back on top of it now but I'm having trouble with merging nodes into a common buss and pulling a line off a bus into a single node. I don't remember having this problem before the accident but now everything I do doesn't work the way I remembered. At first I thought I just wasn't reading the help and tutorial info right, but then I tried some files that I had done before the accident and they all worked like I thought they should. So now I'm not sure what's wrong.  

  I've tried to isolate the problem as much as I can. I hope my description is clear enough. If anyone is interested I can email the files. Here is the info on a mock design that demonstrates the problem(at least one of them anyway):  I'm developing using BDF files in the Block Diagram/ Schematic editor.  I have a Top-Level file which calls a sub file which has only 3 pins a Data Input Pin, a Clock Pin and a 4 bit wide Data Output Buss. The sub file is just 4 D Flip Flops wired as a serial input parallel output. The output bus Pin is named D[3..0], it is fed by a Bus Line(this is the problem line). The output of each Flip Flop feeds a node line which are labeled D3, D2, D1, D0 respectively.   If I name the bus feeding the output bus pin D[3..0] I get this warning:  Warning: Pin "D[3..0]" is missing source Warning: Pin "BCLK" not connected Warning: Pin SIN not connected  A problem with all of my I/Os  Double clicking on the first error highlights the problem bus line, named D[3..0]  If I then rename the same bus D3,D2,D1,D0  Everything compiles fine and the simulations are exactly what I would expect.  The output bus pin is named D[3..0] in either case the only change is renaming that one bus feeding the output pin.  Just as an added piece of information, I can modify the older files and they work as I would expect regardless of the naming conventions used or how they are modified. All the new files I've created have this problem.   Any thoughts would be greatly appreciated.  Steve

[Altera_Forum]

I'm just guessing, but I always name bus nodes with brackets operators I believe Quartus wants these. So use D[3] instead of D3. This is backwards from Orcad schematics which goofs me up sometimes.

[Altera_Forum]

--- Quote Start ---  I'm working on a project that I almost had done about four months ago, but then I had an accident that kept me from working. I'm getting back on top of it now but I'm having trouble with merging nodes into a common buss and pulling a line off a bus into a single node. I don't remember having this problem before the accident but now everything I do doesn't work the way I remembered. At first I thought I just wasn't reading the help and tutorial info right, but then I tried some files that I had done before the accident and they all worked like I thought they should. So now I'm not sure what's wrong.    I've tried to isolate the problem as much as I can. I hope my description is clear enough. If anyone is interested I can email the files. Here is the info on a mock design that demonstrates the problem(at least one of them anyway):  I'm developing using BDF files in the Block Diagram/ Schematic editor.  I have a Top-Level file which calls a sub file which has only 3 pins a Data Input Pin, a Clock Pin and a 4 bit wide Data Output Buss. The sub file is just 4 D Flip Flops wired as a serial input parallel output. The output bus Pin is named D[3..0], it is fed by a Bus Line(this is the problem line). The output of each Flip Flop feeds a node line which are labeled D3, D2, D1, D0 respectively.   If I name the bus feeding the output bus pin D[3..0] I get this warning:  Warning: Pin "D[3..0]" is missing source Warning: Pin "BCLK" not connected Warning: Pin SIN not connected  A problem with all of my I/Os  Double clicking on the first error highlights the problem bus line, named D[3..0]  If I then rename the same bus D3,D2,D1,D0  Everything compiles fine and the simulations are exactly what I would expect.  The output bus pin is named D[3..0] in either case the only change is renaming that one bus feeding the output pin.  Just as an added piece of information, I can modify the older files and they work as I would expect regardless of the naming conventions used or how they are modified. All the new files I've created have this problem.   Any thoughts would be greatly appreciated.  Steve  --- Quote End ---    Hi,  can post your project or schemtic in the forum ?  Kind regards  GPK

[Altera_Forum]

Thanks for looking and responding to this. I have isolated it even more and found one line in the .bdf file that is different between files that work and those that do not. After the copyright info at the top of the file the files that do NOT work have this line: 

 //#pragma file_not_in_maxplusii_format  Files that work do not have that line. If I delete that line in the bdf file with a text editor, the file then works fine. Somewhere there is a software switch that needs to be changed so that when I create new bdf files the offending line does not get generated. For now at least I can delete that line to make things work, but that obviously is kludgy and not a real solution.  Thanks again  Steve