CLOCK_50 was determined to be clock but was found without an associated clock assign.

[Altera_Forum]

Hello,  

 I am having an issue in combining two clocks signals in one project. I am using DE2 Altera board. I am also using Nios processor. So, basically I am trying to merge to independently working projects into one and build my thing on it. I have one clock signal 50MHz for one project and I have another 27MHz signal for another project. I ported mapped all modules correctly to one project and everything went fine.    But then I am not getting what I wanted when programming my FPGA. I am getting the following warnings:    CLOCK_50 was determined to be clock but was found without an associated clock assignment.  PLL1|altpll_component|PLL|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of :20.00 PLL2|altpll_component|PLL|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of :20.00   Someone have an idea on this?   Thanks!

[Altera_Forum]

Have you made a constraints (.sdc) file? If not you will need to in order to tell Quartus what clocks you have and at what frequency. 

 An example minimal SDC file would be the following:  set_time_format -unit ns -decimal_places 3 # ############################################################################## Create Input reference clocks create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } # ############################################################################## Now that we have created the custom clocks which will be base clocks,# derive_pll_clock is used to calculate all remaining clocks for PLLs derive_pll_clocks -create_base_clocks derive_clock_uncertainty