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Calibration clock problem in QSYS

Altera_Forum
Honored Contributor II
‎05-23-2011 02:19 PM
1,036 Views

Hi, 

 

I have recently migrated from SOPC builder to QSYS. However in Quartus II v11.0 I am encountering problems with the PCIe core. I have exported all the signals from the pcie_hard_core to the top level and I get the error 

 

"Input port CLK of GXB Calibration block atom.... cal_blk0 is not connected" 

 

I have checked and verified that the clocks for all the other components like Triple Speed Ethernet, Seriallite II are the PCIe are connected to same clocks. 

 

 

Can someone help me with this problem? 

 

 

Thanks, 

 

Kailash
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