I'm trying to run Quartus from the command line like this:
quartus_map my_project --source=model.v --family=MAXV
Unfortunately, it seems that the project name (my_project) must match the top level module from my source. Is there any way to run quartus from the command line where the top level module is auto-detected so it does not have to be explicitly specified?
Other synthesis flows, like Yosys, automatically detect the top level. For example, for this fsm design:
http://www.edaplayground.com/s/4/496 Yosys log outputs:
Parsing Verilog input from `design.v' to AST representation.
Generating RTLIL representation for module `\fsm'.
