Can We Specify Cut Timing Path Along With The Code?

[Altera_Forum]

Hello, 

 I have a toggle synchronizer like below and want to exclude the domain crossing register transfer ce_t1 <= ce_toggle from timing analysis. is there any way to do it automatically, e.g. by a synthesis attribute or a script, without picking up individual code instances after synthesis? 

[Altera_Forum]

Something like 

attribute altera_attribute : string; attribute altera_attribute of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to "";" & "-name SDC_STATEMENT ""set_false_path -to """;