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So here is the code of my Verilog program:
module measure(clk, in,out); input clk; input signed [11:0] in; output signed [13:0] out; reg [6:0] n; reg [3:0] cnt; wire signed [13:0] out; reg [13:0] counter; assign out=~counter; initial cnt<=4'b0000; always @(posedge clk) begin if(n[6]==1'b1) begin n=7'b0000000; counter[13:10]<={1'b0,(cnt[2:0])}; cnt<=4'b0000; end if(n[6]==1'b0) begin cnt<=4'b1111; end n<=n+1; end endmodule for this version of the program everything goes as planned and the output is negative(2's complement) but if I substitue n=7'b00000000; with n<=7'b0000000; the output becomes 0, can someone please explain this for me? Thanks in advanceLink Copied
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This is a common thing in Verilog, the blocking(=) vs. non blocking(<=) assignment. Blocking assignment takes effect immediately (means the next line statement will be evaluated based on the new value) but non-blocking assignment takes effect at the end of the always block (means the new value can only be seen at the next positive edge of clk).
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Thanks, but I actually don't see how this, explains this specific situation. Can you please provide a more detalieted explanation?
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--- Quote Start --- if I substitue n=7'b00000000; with n<=7'b0000000; the output becomes 0, can someone please explain this for me? --- Quote End --- I can't reproduce the said behaviour. I guess, you observed it with a different piece of code. There will be of course behavioral differences related to blocking versus non-blocking assignment, as already explained. n<=7'b0000000 will be ignored, because it's overwritten by n <= n +1 On the other hand it's a really bad coding style to combine blocking and non-blocking assignents for the same variable, as done in the original code for n. This causes at least confusion of the reader (and most likely the author too), and might be non-synthesizable in some cases. The pitfalls of blocking assignments are visually described in the classical Cummings paper: http://www.sunburst-design.com/papers/cummingssnug2000sj_nba.pdf

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