I'm having a hard time satisfying Quartus II design assistant rule D102: "multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain." See here (http://quartushelp.altera.com/12.1/mergedprojects/verify/da/comp_file_rules_synch.htm) for more info.
This is only a "medium" violation, but I'd still like to get rid of it. I'm not really sure how this rule is even implemented, will it always assume that all bits in any vector are supposed to be interpreted together? And does it really detect that the way you are transferring a vector to another clock domain is safe, or are you just supposed to ignore the violation in code you know to be safe?
We're currently using clock crossing module with a req-busy type interface that is carefully designed and should be very safe. Still it will trigger rule D102, but not D101. If the answer to my question above is yes, is there an example somewhere of how to design a module for crossing vectors from one clock domain to another without causing any design assistant violations?
