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Altera_Forum
Honored Contributor I
826 Views

Can't Simulate Buffer port in ModelSim

Hello everyone, I have the following simple VHDL code for clock frequency division: 

 

 

 

---------------------- Frequency division using Variables ------------------- 

LIBRARY ieee; 

USE ieee.std_logic_1164.all; 

----------------------------------------- 

ENTITY freq_divider IS 

PORT ( clk : IN STD_LOGIC; 

out2 : BUFFER STD_LOGIC); 

END freq_divider; 

----------------------------------------- 

ARCHITECTURE example OF freq_divider IS 

BEGIN 

PROCESS (clk) 

VARIABLE count2 : INTEGER RANGE 0 TO 7; 

BEGIN 

IF (clk'EVENT AND clk='0') THEN 

count2 := count2 + 1; 

IF (count2 = 3) THEN 

out2 <= NOT out2; 

count2 := 0; 

END IF; 

END IF; 

END PROCESS; 

END example; 

----------------------------------------- 

 

 

But when I try to Simulate it with modelsim-altera the (out2) signal does not give me any value. I was wondering is it because the port is assigned as (buffer)????? Please help me. Thanks
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2 Replies
Altera_Forum
Honored Contributor I
45 Views

Did you provide a clock on the clock port?

Altera_Forum
Honored Contributor I
45 Views

Hi, 

 

with "does not give any value" I assume you mean 'U'? If so, it's because you never initialize "out2" to any value. 

 

Also, I agree with Tricky, you need a testbench that provides a clock. If you don't know about testbenches, Google has plenty of examples, e.g. here: https://www.doulos.com/knowhow/vhdl_designers_guide/test_benches_part_1/ (https://www.doulos.com/knowhow/vhdl_designers_guide/test_benches_part_1/). 

 

Best regards, 

GooGooCluster
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