Can't place multiple pins assigned JTAG shared pins

[enovara]

Hello,

I followed all the rules in:

•  https://www.altera.com/en_us/pdfs/literature/hb/max-10/ug_m10_config.pdf 
• https://www.intel.com/content/www/us/en/docs/programmable/683865/current/guidelines-dual-purpose-configuration-pin.html

During the Compile I still have the Error: Can't place multiple pins assigned JTAG shared pins

(as  an example in https://community.intel.com/t5/Intel-Quartus-Prime-Software/Error-176310-Can-t-place-multiple-pins-JTAG-Sharing/td-p/27941?profile.language=it)

Max10 on Quartus 18.0 

If i follow the guidelines I could be able top open  assignment-->Device-->Device and Pins Options-->Dual-purpose pins , but the config scheme is "Internal Configuration" and the "Dual-purpose Pins" tab is empty. (So, I can not follow this solution: https://forums.opalkelly.com/t/multiple-pin-assignments-error/1336)

Additional: it won't allow dual-use whilst signalTap is enabled (done!)

May I have to fix more sw/cad setting to fit the design with the dual port ?

Any help would be greatly appreciated. 

[FvM]

Which pin locations can't be used?

[enovara]

All 4 pins for jtag (tdi, tdo, tck and tms)

[lixy]

Hi,

I just tried a very simple project with Quartus 18.0std and assigned one output pin to the JTAG TCK pin. The compilation is ok.

Could you check again whether you have selected the "Enable JTAG pin sharing" in the "Device and Pin Options“ --> ”General” tab?

Best Regards,

Xiaoyan

[enovara]

Hi,

thanks for the feedback.

1) This is how i try to configure my system:

What I am seeing is that your design is using one of the JTAG pins as a general purpose I/O pin.
Our requirement is different: we need to use the JTAG pins as a JTAG interface while the JTAG_EN is logic high, and then, after the initial configuration, those same pins would be used as I/O pins (while JTAG_EN is logic low).

Is this doable on the MAX10 board?

What you are doing seems to be different: you are re-assigning one of the jtag pins to a custom function.

2) I am not able to open the " dual-purpose pins " tab; this is what Quartus is showing me: 

[lixy]

Hi,

For MAX 10 device, you only need to check chapter 3.1. Dual-Purpose Configuration Pins in MAX® 10 FPGA Configuration User Guide. This chapter didn't mention any actions you need to take in the "dual-purpose pin" tab.

As you can see from 3.1.1.1. JTAG Pin Sharing Behavior, when you enable " JTAG Pin Sharing" in the General tab:

• During Configuration, these pins are dedicated JTAG pins.
• During User mode, these pins can switch between dedicated JTAG pins and user I/O by control the JTAGEN signal.

As you can see these "altera_reserve_tms"... pins in Pin Planner, I think you have probably instantiated JTAG related ip in your design. This would be the major reason you see the error.

You can see the following Note in Table 25 of 3.1.1. Guidelines: Dual-Purpose Configuration Pin.

"The Signal Tap logic analyzer IP, JTAG-to- Avalon® master bridge IP, and other JTAG-related IPs cannot be used if you enable the JTAG pin sharing feature in your design."

For example, when I add In-system source and probe IP to my design, and I assign GPIO to TCK, the fitter will report the failure. 

Best Regards,

Xiaoyan