Can't resolve multiple constant drivers?

[Altera_Forum]

Hi, ive been trying to compile the code below in quartus II v9.0 and i get the following error message Error (10028): Can't resolve multiple constant drivers for net "LSD_SEG[0]" at KEYBOARD.VHD(385)

ive tried to solve this since friday, now im out of options. the problem here is, i assign values to MSD_SEG & LSD_SEG from 3 different processes and quartus doesnt like that. i tried combining processes but only the push buttons (PB1 and PB2) are working and the keyboard isnt. The code compiles fine in Maxplus II but the thing is, Maxplus II doesnt support EP2C20F484CN FPGA (Cyclone II development board DE1). pls help 

[Altera_Forum]

I can´t find the signal LSD_SEG in the code you posted. 

But one of the rules of VHDL is that you cannot assign a signal in more than one place. This error is a result of you assigning a value to the specified signal in more than one place.   Check that you are not assigning this signal outside of a process and inside, or in two or more different processes or in two or more different places outside of a process.   Right clicking on the warning in Quartus and clicking help, should help you to understand why you get this error.

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

--- Quote Start ---  I can´t find the signal LSD_SEG in the code you posted. But one of the rules of VHDL is that you cannot assign a signal in more than one place. This error is a result of you assigning a value to the specified signal in more than one place.   Check that you are not assigning this signal outside of a process and inside, or in two or more different processes or in two or more different places outside of a process.   Right clicking on the warning in Quartus and clicking help, should help you to understand why you get this error.  --- Quote End ---    My bad, the signals are LSD_7SEG & MSD_7SEG. That's exactly what my problem is, im assigning a signal in more than one place. hw can i not do that and still achieve the desired results?  Thanx for quick response  Regards Dante

[Altera_Forum]

--- Quote Start ---  Hi,  I'm not a real VHDl expert, but as far as I know is the "'EVENT" only allowed for single bits. 'EVENT on vector is not syntheziable. Why not using a PROCESS with a sensitivity list ?  Your assign values to MSD_7SEG and LSD_7SEG in three different processes. That causes the multiple driver error. You have to combine the processes to one. Additinonal you have two wait statements in one process, which is also not allowed.  Kind regards  GPK  --- Quote End ---    At pletz, ive already changed that "event" part, thank you. I tried combining the processes. it compiles but doesnt work as it should. this code works superbly on the UP2 board. Can you show me exactly to combine the processes?   Regards Dante

[Altera_Forum]

Both verilog and VHDL only allow you to write to a signal from a single process.

[Altera_Forum]

--- Quote Start ---  I tried combining the processes. it compiles but doesnt work as it should.  --- Quote End ---   Sounds plausible. Combining the processes creates legal VHDl semantic, but not necessarily intended behaviour. The basic problem is, that you have to resolve the conflicting assignments logically. Whatever code you write, you have to know which of the multiple signal assignments should be in effect at different times. The design compiler will resolve the conflict only based on code placement. The last assignment wins.

[Altera_Forum]

--- Quote Start ---  Sounds plausible. Combining the processes creates legal VHDl semantic, but not necessarily intended behaviour. The basic problem is, that you have to resolve the conflicting assignments logically. Whatever code you write, you have to know which of the multiple signal assignments should be in effect at different times. The design compiler will resolve the conflict only based on code placement. The last assignment wins.  --- Quote End ---    I even tried using a multiplexer, both parts work but the one part is not displayed. for example, when i press the push button, 7 seg displays, display the contents stored for push button event but when i release it, last key pressed on the keyboard is displayed and thats not how it should work.   This is how it should work:  1. when i press a key on the keyboard, the contents associated with that key should be displayed and stay displayed.  2. when i press the push button, the contents associated with push button counter should be displayed and stay displayed.   3. (1) and (2) work fine independently, problem arises when i put them in a single file.  im new to vhdl and like i said, i've been trying to resolve this since friday and this project is due tomorrow. please help pls. i've attached a more readable code, pls help me correct it.:confused:    Regards Dante

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

Aside from multiple drivers, a huge problem you're going to have is your clocking scheme. 

 You have generated your own clock using logic, and you are clocking other processes with that logic generated clock. In FPGAs, this is a big problem as it can cause all sorts of timing issues. Its much better to generate an enable for registers that are clocked from the source clock.

[Altera_Forum]

--- Quote Start ---  Aside from multiple drivers, a huge problem you're going to have is your clocking scheme.  You have generated your own clock using logic, and you are clocking other processes with that logic generated clock. In FPGAs, this is a big problem as it can cause all sorts of timing issues. Its much better to generate an enable for registers that are clocked from the source clock.  --- Quote End ---    Hi tricky, can you pls help with some form of example? the cyclone II DE1 board didnt have any timing issues so i didnt think that would be a problem. The clock that ive generated is only used by the push button process (i think), coz the keyboard has clock conneted to it already.  I been with vhdl for 2 weeks now, so everything is just new to me. :(

[Altera_Forum]

No Problem. with VHDL you can write whatever VHDL you want and have it simulate fine, but if it isnt written with recommended coding styles you cant guarantee that the synthesised firmware will work.  

 Did you set any timing requirements when you say it doesnt throw any warnings?   For all VHDL you are going to synthesize, the recommended style for a clock process (to generate registers) is this:   reg_proc : process(clk, reset) begin if reset = '1' then --asynchronous reset elsif rising_edge(clk) then --registered statements go here if enable = '1' then --register with enable statements go here end if; end if; end process;   Using wait statements in process is allowed, but not a common form. It can be safer to use the rising_edge(clk) method above, because more people will have seen it and I know all synthesisors will work with it. Use wait statements to your hearts content in testbenches (where they can be very useful for creating bus functional models).  As you are new to VHDL, can I also recommend you stop using std_logic_arith and std_logic_signed/unsigned now. They are non-standard packages. They have become a bit of a defacto standard. The real IEEE standard is numeric_std, which I recommend using over the other 2 packages. it allows you to do signed and unsigned arithmatic in the same file (the other method does not) and with proper typing and much better named functions it makes more sense. It is also compatible with the new standardised fixed point libraries for doing really easy fixed point maths.  Another thing to remember is that internal ports on entites (ie. ones that dont connect to pins) can be any type you want - so use integers/boolean/enummerated types to make your code much more readable.  Any other questions, please ask away.

[Altera_Forum]

--- Quote Start ---  No Problem. with VHDL you can write whatever VHDL you want and have it simulate fine, but if it isnt written with recommended coding styles you cant guarantee that the synthesised firmware will work.   Did you set any timing requirements when you say it doesnt throw any warnings?   For all VHDL you are going to synthesize, the recommended style for a clock process (to generate registers) is this:   reg_proc : process(clk, reset) begin if reset = '1' then --asynchronous reset elsif rising_edge(clk) then --registered statements go here if enable = '1' then --register with enable statements go here end if; end if; end process;   Using wait statements in process is allowed, but not a common form. It can be safer to use the rising_edge(clk) method above, because more people will have seen it and I know all synthesisors will work with it. Use wait statements to your hearts content in testbenches (where they can be very useful for creating bus functional models).  As you are new to VHDL, can I also recommend you stop using std_logic_arith and std_logic_signed/unsigned now. They are non-standard packages. They have become a bit of a defacto standard. The real IEEE standard is numeric_std, which I recommend using over the other 2 packages. it allows you to do signed and unsigned arithmatic in the same file (the other method does not) and with proper typing and much better named functions it makes more sense. It is also compatible with the new standardised fixed point libraries for doing really easy fixed point maths.  Another thing to remember is that internal ports on entites (ie. ones that dont connect to pins) can be any type you want - so use integers/boolean/enummerated types to make your code much more readable.  Any other questions, please ask away.  --- Quote End ---     Ohk Tricky thanx. i get the timing warnings but they dont matter for now because ive tested both keyboard process and push button processes independently and they work fine. the problem is to get them to work together. can you please help me with that? look at the code and try to see what can be done to resolve the issue. pls try to compile it, ull see what im talking about.   Regards Dante