Can't use testbench in Modelsim - error loading design

[Altera_Forum]

Hi everyone, 

 First I want to say that I searched all the threads here, and while this is a common problem, I could not figure out how to solve it.  I am trying to use a small testbench I wrote using the Quartus testbench template writer, but I am getting this error:  ** Error: (vsim-3170) Could not find 'C:/Users/nettek/QuartusProjects/Final Project - 11.3.16 - par/test/simulation/modelsim/rtl_work.tb_test1'.# # Error loading design# Error: Error loading design# Pausing macro execution# MACRO ./Test_run_msim_rtl_vhdl.do PAUSED at line 14  Steps I took: 1. Created a BDF file with two components in it, obviously it has input/output ports and some internal signals. 2. Created an HDL file from the BDF file. Added it to project. Removed the BDF file from project (did not delete it). 3. Created a testbench using the Quartus template writer. 4. Added the VHT file to project. 5. Took to Assignments -> Settings -> EDA tool settings -> Simulation -> Chose compile test bench and chose the VHT file. 6. Tools -> Run simulation tool -> RTL simulation which opened Modelsim.  Of course I always made sure to compile whenever I needed to.  I don't understand this problem, just two days ago it didn't happen and now it does. What could be the problem?  Also, I would appreciate if you could tell me how to test internal signals of a BDF file in Modelsim using a testbench. I know that I can give the signals names, turn the BDF file into a HDL file and then compile it in Modelsim, and then force the signals, but I want to use a testbench to make this be automatic. Problem is, using a testbench, I only see the input/outputs.  Thank you!

[Altera_Forum]

I don't think modelsim will work if there are spaces or characters that are illegal for linux anywhere in your path. Try renaming your directory "FinalProject_11.3.16_par" and see if that works. You will need to update your project file as well. BTW, I like to write dates like 20160311 so that a series of dated files will sort correctly.

[Altera_Forum]

Thanks for your answer. Unfortunately changing the folder name did not help (I didn't think it would, as this thing worked before with the previous folder name), though I'm not sure what you meant by updating project file. 

 Anyway, I have to say that despite this not working, I can actually go to work/rtl_work from Modelsim, right click the VHT file and simulate. The test bench is working correctly, it seems. But I have another problem.

[Altera_Forum]

--- Quote Start ---   I don't understand this problem, just two days ago it didn't happen and now it does. What could be the problem?   --- Quote End ---    This looks like theres files missing in MODELSIM. I suggest driving modelsim yourself and not relying on Quartus to do this for you. The commands are very straightforward. If you have files a.vhd and b.vhd with the top level entity called "testbench" inside a.vhd, then all you need to do is this in the modelsim console:  vcom a.vhd vcom b.vhd vsim testbench  (use vlog instead of vcom for verilog files).    --- Quote Start ---   Also, I would appreciate if you could tell me how to test internal signals of a BDF file in Modelsim using a testbench. I know that I can give the signals names, turn the BDF file into a HDL file and then compile it in Modelsim, and then force the signals, but I want to use a testbench to make this be automatic. Problem is, using a testbench, I only see the input/outputs.  Thank you!  --- Quote End ---    BDF files cannot be simulated, so you can only see what is in the generated HDL file. As for driving them, with verilog you can always force/drive any signal within the hierarchy. With VHDL this requires you to use VHDL 2008. But if you need to drive internal signals then I suggest you have a problem with the design - testbenches should only ever drive the DUT io. You can always monitor internal signals on the wave window or log them in your HDL.

[Altera_Forum]

Tricky, thank you. You're right, it's best to open these files in Modelsim itself and not through Quartus. 

 I have actually found a solution to this, I'll post it here in case others run into the same problems: (assuming vhdl and not verilog)  1. If you have a BDF file like me, use Quartus to create an HDL file from it (file -> create/update -> create HDL file...) 2. Open a project in modelsim 3. Add all the vhd files in your design, include of course the main HDL file 4. Open the main HDL file so that the code appears (you can edit it, etc.) 5. In the menu, click on source -> show language templates 6. In the new window that just opened, double click create testbench 7. Write your testbench code 8. Compile the files, click simulate, and choose to simulate the testbench file in your work library