Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Can't we use Generics in Avalon-MM slave interface template?

Altera_Forum
Honored Contributor II
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I had my system working. My system is in VHDL, now I am adding Generic declaration in entity declaration. The file can be synthesised. However, when I compile, I get error complaining the size of my signals are not right. I feel that the generic setting is not working, the signals have the length I set before I added generic declaration. 

Has anyone experienced this before? 

 

Thanks:)
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